Freescale Semiconductor MPC5565, Reference Manual

Page: 743 / 1153

Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
18-44 Freescale Semiconductor
18.4 Functional Description
The eQADC provides a parallel interface to two on-chip ADCs, and a single master to single slave serial
interface to an off-chip external device. The two on-chip ADCs are architected to allow access to all the
analog channels.
Initially, command data is contained in system memory in a user defined data queue structure. Command
data is moved between the user-defined queues and CFIFOs by the host CPU or by the eDMA which
responds to interrupt and eDMA requests generated by the eQADC. The eQADC supports software and
hardware triggers from other modules or external pins to initiate transfers of commands from the multiple
CFIFOs to the on-chip ADCs or to the external device.
CFIFOs can be configured to be in single-scan or continuous-scan mode. When a CFIFO is configured to
be in single-scan mode, the eQADC scans the user-defined command queue one time. The eQADC stops
transferring commands from the triggered CFIFO after detecting the EOQ bit set in the last transfer. After
an EOQ bit is detected, software involvement is required to rearm the CFIFO so that it can detect new
trigger events.
When a CFIFO is configured for continuous-scan mode, the whole user command queue is scanned
multiple times. After the detection of an asserted EOQ bit in the last command transfer, command transfers
can continue or not depending on the mode of operation of the CFIFO.
The eQADC can also in parallel and independently of the CFIFOs receive data from the on-chip ADCs or
from off-chip external device into multiple RFIFOs. Result data is moved from the RFIFOs to the
user-defined result queues in system memory by the host CPU or by the eDMA.
18.4.1 Data Flow in the eQADC
Figure 18-24 shows how command data flows inside the eQADC system. A command message is the
predefined format in which command data is stored in the user-defined command queues. A command
message has 32 bits and is composed of two parts: a CFIFO header and an ADC command. Command
messages are moved from the user command queues to the CFIFOs by the host CPU or by the eDMA as
they respond to interrupt and eDMA requests generated by the eQADC. The eQADC generates these
requests whenever a CFIFO is not full. The FIFO control unit transfers only the command part of the
command message to the ADC. Information in the CFIFO header together with the upper bit of the ADC
command is used by the FIFO control unit to arbitrate which triggered CFIFO transfers the next command.
Because command transfer through the serial interface can take significantly more time than a parallel
transfer to the on-chip ADCs, command transfers for on-chip ADCs occur concurrently with the transfers
through the serial interface. Commands sent to the ADCs are executed in a first-in-first-out (FIFO) basis
Table 18-33. ADC n _OCCR Field Descriptions
Field Description
0–1 Reserved.
2–15
OCC n
[0:13]
ADC n offset calibration constant. Contains the offset calibration constant used to fine-tune ADC n conversion results.
Negative values should be expressed using the two’s complement representation.