Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Time Processing Unit (eTPU)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 17-9
• Two independent 24-bit time bases for channel synchronization
— The first time base can be clocked by the system clock with programmable prescaler division
from 2 to 512 (in steps of 2).
— The first time base can also be clocked by an external signal with programmable prescaler
divisions of 1 to 256.
— The second time base can be clocked by an external signal with programmable prescaler
divisions from 1 to 64 or by the system clock divided by 8.
— The second time base has a programmable prescaler that applies to all TCR2 clock inputs
except the angle counter.
— The second time base counter can work as an angle counter, enabling angle-based applications
to match angle instead of time.
— The second time base can alternatively be used as a pulse accumulator gated by an external
signal.
— Either time base can be written or read by either eTPU engine at any time.
— Either time base can be read, but not written, by the host.
— Both time bases can be exported or imported from engine to engine through the STAC (shared
time and counter) bus.
NOTE
An engine cannot export/import to/from itself. An engine cannot import a
time base and/or angle count if it is in angle mode.
• Event-triggered RISC processor (microengine)
— 2-stage pipeline implementation (fetch and execution), with separate instruction memory
(SCM) and data memory (SDM).
— Two-system-clock microcycle fixed-length instruction execution for the ALU.
— 12 KB of shared code memory (SCM).
— 2.5 KB of shared data memory (SDM)
— Instruction set with embedded channel support, including specialized channel control
subinstructions and conditional branching on channel-specific flags.
— Channel-oriented addressing: channel-bound address mode with host configured channel base
address allows the same function to operate independently on different channels.
— Channel-bound data address space of up to 128 32-bit parameters (512 bytes).
— Global parameter address mode allows access to common channel data of up to 256 32-bit
parameters (1024 bytes).
— Support for indirect and stacked data access schemes.
— Parallel execution of: data access, ALU, channel control and flow control subinstructions in
selected combinations.
— 24-bit registers and ALU, plus one 32-bit register for full-width SDM access.
— Additional 24-bit multiply/MAC/divide unit which supports all signed/unsigned/
multiply/MAC combinations, and unsigned 24-bit divide. The MAC/divide unit works in
parallel with the regular microcode commands.