Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Direct Memory Access (eDMA)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
9-38 Freescale Semiconductor
Channel priority errors are identified within a group after that group has been selected as the active group.
For the example that follows, all of the channel priorities in Group 1 are unique, but some of the channel
priorities in Group 0 are the same:
1. Configure the eDMA for fixed-group and fixed-channel arbitration modes.
2. Group 1 is the highest priority and all channels are unique in that group.
3. Group 0 is the next highest priority and two channels have the same priority level.
4. If Group 1 has service requests pending, those requests are executed.
5. After all Group 1 requests have completed, Group 0 becomes the active group.
6. If Group 0 has a service request, the eDMA selects the undefined channel in Group 0 and generates
a channel priority error.
7. Repeat Step 6 until the all Group 0 requests are serviced or a higher-priority Group 1 request is
received.
In step 2, the eDMA acknowledge lines assert only if the selected channel is requesting service via the
eDMA peripheral request signal. If interrupts are enabled for all channels, an error interrupt is generated.
However, the channel number for the EDMA_ER and the error interrupt request line contain undefined
data because the channel is ‘undefined’. A group priority error is global and any request in any group
causes a group priority error.
If priority levels are not unique, the highest (channel/group) priority that has an active request is selected,
but the lowest numbered (channel/group) with that priority is selected by arbitration and executed by the
eDMA engine. The hardware service request handshake signals, error interrupts and error reporting are
associated with the selected channel.
9.4.3 DMA Request Assignments
The assignments between the DMA requests from the modules to the channels of the eDMA are shown in
Table 9-23 . The source column is written in C language syntax. The syntax is
module_instance.register[bit].
Table 9-23. DMA Request Summary for eDMA
DMA Request Channel Source Description
eQADC_FISR0_CFFF0 0 EQADC.FISR0[CFFF0] eQADC Command FIFO 0 Fill Flag
eQADC_FISR0_RFDF0 1 EQADC.FISR0[RFDF0] eQADC Receive FIFO 0 Drain Flag
eQADC_FISR1_CFFF1 2 EQADC.FISR1[CFFF1] eQADC Command FIFO 1 Fill Flag
eQADC_FISR1_RFDF1 3 EQADC.FISR1[RFDF1] eQADC Receive FIFO 1 Drain Flag
eQADC_FISR2_CFFF2 4 EQADC.FISR2[CFFF2] eQADC Command FIFO 2 Fill Flag
eQADC_FISR2_RFDF2 5 EQADC.FISR2[RFDF2] eQADC Receive FIFO 2 Drain Flag
eQADC_FISR3_CFFF3 6 EQADC.FISR3[CFFF3] eQADC Command FIFO 3 Fill Flag
eQADC_FISR3_RFDF3 7 EQADC.FISR3[RFDF3] eQADC Receive FIFO 3 Drain Flag
eQADC_FISR4_CFFF4 8 EQADC.FISR4[CFFF4] eQADC Command FIFO 4 Fill Flag