Preface
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor
21-33
If the module is disabled during transmission or reception, FlexCAN2 does the following:
•
Waits to be in either idle or bus off state, or else waits for the third bit of intermission and then
checks it to be recessive
•
Waits for all internal activities like move in or move out to finish
•
Ignores its RX input pin and drives its TX pin as recessive
•
Shuts down the clocks to the CPI and MBM sub-modules
•
Sets the NOTRDY and MDISACK bits in CAN
x
_MCR
The bus interface unit continues to operate, enabling the CPU to access memory mapped registers except
the free running timer, the CAN
x
_ECR and the message buffers, which cannot be accessed when the
module is disabled. Exiting from this mode is done by negating the CAN
x
_MCR[MDIS] bit, which will
resume the clocks and negate the CAN
x
_MCR[MDISACK] bit.
21.4.7
Interrupts
The module can generate interrupts from 20 interrupt sources (16 interrupts due to message buffers, one
interrupt due to an error condition, two interrupts for the OR'd MB16–MB31 and MB32–63, and one
interrupt for one of the following: a bus off condition, a transmit warning, or a receive warning).
Each of the 64 message buffers can be an interrupt source, if its corresponding CAN
x
_IMRH or
CAN
x
_IMRL bit is set. There is no distinction between TX and RX interrupts for a particular buffer, under
the assumption that the buffer is initialized for either transmission or reception. Each of the buffers has
assigned a flag bit in the CAN
x
_IFRH or CAN
x
_IFRL registers. The bit is set when the corresponding
buffer completes a successful transmission/reception and is cleared when the CPU writes it to 1.
A combined interrupt for each of two MB groups, MB16–MB31 and MB32–MB63, is also generated by
an OR of all the interrupt sources from the associated MBs. This interrupt gets generated when any of the
MBs generates an interrupt. In this case the CPU must read the CAN
x
_IFRH and CAN
x
_IFRL registers
to determine which MB caused the interrupt.
The other two interrupt sources (bus off/transmit warning/receive warning and error) generate interrupts
like the MB interrupt sources, and can be read from CAN
x
_ESR. The bus off/transmit warning/receive
warning and error interrupt mask bits are located in the CAN
x
_CR.
21.4.8
Bus Interface
The CPU access to FlexCAN2 registers are subject to the following rules:
•
Read and write access to unimplemented or reserved address space also results in access error. Any
access to unimplemented MB locations results in access error.
•
For a FlexCAN2 configuration that uses less than the total number of MBs and MAXMB is set
accordingly, the remaining MB and RX mask register spaces can be used as general-purpose RAM
space. Byte, word and long word accesses are allowed to the unused MB space.
NOTE
Unused MB space must not be used as general purpose RAM while
FlexCAN is transmitting and receiving CAN frames.
Summary of Contents for MPC5565
Page 18: ...MPC5565 Microcontroller Reference Manual Devices Supported MPC5565 MPC5565 RM Rev 1 0 09 2007...
Page 34: ...MPC5565 Reference Manual Rev 1 0 Freescale Semiconductor 15...
Page 35: ...MPC5565 Reference Manual Rev 1 0 16 Freescale Semiconductor...
Page 553: ...Flash Memory MPC5565 Microcontroller Reference Manual Rev 1 0 13 38 Freescale Semiconductor...
Page 559: ...SRAM MPC5565 Microcontroller Reference Manual Rev 1 0 14 6 Freescale Semiconductor...
Page 973: ...Preface MPC5565 Microcontroller Reference Manual Rev 1 0 21 36 Freescale Semiconductor...
Page 1153: ...Calibration MPC5565 Microcontroller Reference Manual Rev 1 0 B 8 Freescale Semiconductor...
