External Bus Interface (EBI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
12-18
Freescale Semiconductor
12.3.1.6
EBI Base Registers 0–3 (EBI_BR
n
) and EBI Calibration Base Registers
0–3 (EBI_CAL_BR
n
)
The EBI_BR
n
are used to define the base address and other attributes for the corresponding chip select.
The EBI_CAL_BR
n
are used to define the base address and other attributes for the corresponding
calibration chip select.
The following table describes the fields in the EBI calibrations base register:
Address: Base + 0x0010 (EBI_BR0)
Base + 0x0018 (EBI_BR1)
Base + 0x0020 (EBI_BR2)
Base + 0x0028 (EBI_BR3)
Base + 0x0040 (EBI_CAL_BR0)
Base + 0x0048 (EBI_CAL_BR1)
Base + 0x0050 (EBI_CAL_BR2)
Base + 0x0058 (EBI_CAL_BR3)
Access: R/W
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
1
BA
W
Reset
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
BA
0
0
0
PS
0
0
0
0
BL
WEBS TBDIP
0
0
BI
V
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Figure 12-5. EBI Base Registers 0–3 (EBI_BR
n
) and EBI Calibration Base Registers 0–3 (EBI_CAL_BR
n
)
Table 12-10. EBI_BR
n
and EBI_CAL_BR
n
Field Descriptions
Field
Description
0–16
BA
[0:16]
Base address. Compared to the corresponding unmasked address signals among ADDR[0:16] of the internal
address bus to determine if a memory bank controlled by the memory controller is being accessed by an internal
bus master.
Note:
The upper 3 bits of the base address (BA) field, EBI_BR
n
[0:2], and EBI_CAL_BR
n
[0:2], are tied to a fixed
value of 001. These bits reset to their fixed value.
17–19
Reserved.
20
PS
Port size. Determines the data bus width of transactions to this chip select bank.
1
0 32-bit port
1 16-bit port
Note:
The calibration port size must be 16-bits wide.
21–24
Reserved.
25
BL
Burst length. Determines the amount of data transferred in a burst for this chip select, measured in 32-bit words. The
number of beats in a burst is automatically determined by the EBI to be 4, 8, or 16 according to the port size so that
the burst fetches the number of words chosen by BL.
0 8-word burst length
1 4-word burst length
Summary of Contents for MPC5565
Page 18: ...MPC5565 Microcontroller Reference Manual Devices Supported MPC5565 MPC5565 RM Rev 1 0 09 2007...
Page 34: ...MPC5565 Reference Manual Rev 1 0 Freescale Semiconductor 15...
Page 35: ...MPC5565 Reference Manual Rev 1 0 16 Freescale Semiconductor...
Page 553: ...Flash Memory MPC5565 Microcontroller Reference Manual Rev 1 0 13 38 Freescale Semiconductor...
Page 559: ...SRAM MPC5565 Microcontroller Reference Manual Rev 1 0 14 6 Freescale Semiconductor...
Page 973: ...Preface MPC5565 Microcontroller Reference Manual Rev 1 0 21 36 Freescale Semiconductor...
Page 1153: ...Calibration MPC5565 Microcontroller Reference Manual Rev 1 0 B 8 Freescale Semiconductor...