Freescale Semiconductor MPC5565, Reference Manual

Page: 769 / 1153

Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
18-70 Freescale Semiconductor
(EQADC_FISRn) ”). The SSS bit is set by writing 1 to the single-scan enable bit, EQADC_CFCRn[SSE]
(see Section 18.3.2.6, “eQADC CFIFO Control Registers 0–5 (EQADC_CFCRn) ”).
In single-scan edge or level trigger mode, the respective triggers are only detected when the SSS bit is
asserted. When the SSS bit is negated, all trigger events for that CFIFO are ignored. Writing a 1 to the SSE
bit can be done during the same write cycle that the CFIFO operation mode is configured.
Only the eQADC can clear the SSS bit. After SSS is asserted, it remains asserted until the eQADC
completes the command queue scan, or the CFIFO operation mode, EQADC_CFCRn[MODE
n ] (see
Section 18.3.2.6) is changed to disabled. The SSS n bit is negated while MODE n is disabled.
Single-Scan Software Trigger
When single-scan software trigger mode is selected, the CFIFO is triggered by an asserted SSS bit. The
SSS bit is asserted by writing 1 to the SSE bit. Writing to SSE while SSS is already asserted does not have
any effect on the state of the SSS bit, nor does it cause a trigger overrun event.
The CFIFO commands start to be transferred when the CFIFO becomes the highest priority CFIFO using
an available on-chip ADC or an external command buffer that is not full. When an asserted EOQ bit is
encountered, the eQADC clears the SSS bit. Setting the SSS bit is required for the eQADC to start the next
scan of the queue.
The pause bit has no effect in single-scan software trigger mode.
Single-Scan Edge Trigger
When SSS is asserted and an edge triggered mode is selected for a CFIFO, an appropriate edge on the
associated trigger signal causes the CFIFO to become triggered. For example, if rising-edge trigger mode
is selected, the CFIFO becomes triggered when a rising edge is sensed on the trigger signal. The CFIFO
commands start to be transferred when the CFIFO becomes the highest priority CFIFO using an available
on-chip ADC, or an external command buffer that is not full.
When an asserted EOQ bit is encountered, the eQADC clears SSS and stops command transfers from the
CFIFO. An asserted SSS bit and a subsequent edge trigger event are required to start the next scan for the
CFIFO. When an asserted pause bit is encountered, the eQADC stops command transfers from the CFIFO,
but SSS remains set. Another edge trigger event is required for command transfers to continue. A trigger
overrun happens when the CFIFO is in a TRIGGERED state and an edge trigger event is detected.
Single-Scan Level Trigger
When SSS is asserted and a level gated trigger mode is selected, the input level on the associated trigger
signal puts the CFIFO in a TRIGGERED state. When the CFIFO is set to high-level gated trigger mode,
a high level signal opens the gate, and a low level closes the gate. When the CFIFO is set to low-level gated
trigger mode, a low level signal opens the gate, and a high level closes the gate. If the corresponding level
is already present, setting the SSS bit triggers the CFIFO. The CFIFO commands start to be transferred
when the CFIFO becomes the highest priority CFIFO using an available on-chip ADC or an external
command buffer that is not full.
The eQADC clears the SSS bit and stops transferring commands from a triggered CFIFO when an asserted
EOQ bit is encountered or when CFIFO status changes from triggered due to the detection of a closed gate.