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Enhanced Queued Analog-to-Digital Converter (eQADC)

MPC5565 Microcontroller Reference Manual, Rev. 1.0

Freescale Semiconductor

18-63

Figure 18-36. CFIFO Entry Pointer Example

18.4.3.2

CFIFO Prioritization and Command Transfer

The CFIFO priority is fixed according to the CFIFO number. A CFIFO with a smaller number has a higher
priority. When commands of distinct CFIFOs are bound for the same destination (the same on-chip ADC),
the higher priority CFIFO is always served first. A triggered, not-underflowing CFIFO starts to transfer
commands when the following occur:

•

Its commands are bound for an internal command buffer that is not full, and it is the highest priority
triggered CFIFO sending commands to that buffer.

First In

Transfer
Next
Data
Pointer

Last In

Push

Next

Data

Pointer

CFIFO

n

Transfer
Next
Data
Pointer

Push

Next

Data

Pointer

CFIFO

n

First In

Transfer
Next
Data
Pointer

Last In

Push

Next

Data

Pointer

CFIFO

n

After Reset or

Invalidation

Some Entries Pushed

but None Executed

No Entries Pushed

but Some Executed

First In

Transfer
Next
Data
Pointer

Push

Next

Data

Pointer

CFIFO

n

Transfer
Next
Data
Pointer

Push

Next

Data

Pointer

CFIFO

n

First In

Transfer
Next
Data
Pointer

Last In

Push

Next

Data

Pointer

CFIFO

n

No Entries Pushed

but Some Executed

Some Entries Pushed

and Some Executed

Entries Pushed Until

Full and None Executed

First In

Last In

Last In

Valid Entry
Empty Entry

NOTE:

n

= 0, 1, 2, 3, 4, 5

«
...
760
761
762
763
764
...
»

Summary of Contents for MPC5565

Page 1: ...rved Freescale Semiconductor MPC5565RM Rev 1 1 05 2012 This MPC5565 Reference Manual set consists of the following files MPC5565 Reference Manual Addendum Rev 1 MPC5565 Microcontroller Reference Manua...

Page 2: ...PC5565 Preliminary Microcontroller Reference Manual order number MPC5565RM For convenience the addenda items are grouped by revision Please check our website at http www freescale com powerarchitectur...

Page 3: ...ange one row in the table to correct information about eSCI COMBTX DMA request Only the Transmit Data Register Empty and LIN Transmit Data Ready flags drive the DMA request The Transmit Complete flag...

Page 4: ...y adding underscore PBRIDGEA becomes PBRIDGE_A PBRIDGEB becomes PBRIDGE_B Only two rows of the table are changed Table 1 MPC5565RM Rev 1 0 addendum continued Location Description Hardware Vector Mode...

Page 5: ...bridge A master privilege control register PBRIDGE_A_MPCR 32 bit Base 0x0000 Reserved Base 0x0004 0x001F Peripheral bridge A peripheral access control register 0 PBRIDGE_A_PACR0 32 bit Base 0x0020 Re...

Page 6: ...eral bridge B peripheral access control register 0 PBRIDGE_B_PACR0 32 bit Base 0x0020 Reserved Base 0x0024 0x0027 Peripheral bridge B peripheral access control register 2 PBRIDGE_B_PACR2 32 bit Base 0...

Page 7: ...Addendum for Revision 1 0 Freescale Semiconductor 6 Figure 16 13 Unified Channel Block Diagram Page 16 26 Reverse the arrow between the Programmable Filter and Edge Detect Table 1 MPC5565RM Rev 1 0 a...

Page 8: ...ference Manual Addendum Rev 2 Freescale Semiconductor 7 Section13 3 Page 13 4 Remove cross reference to Table 13 2 Add the following table and update the cross reference Table 1 MPC5565RM Rev 1 0 adde...

Page 9: ...5RM Rev 1 0 addendum continued Location Description eMIOS Channel DMA 0 DMA 1 0 Interrupt DMA request 1 Interrupt DMA request 2 Interrupt DMA request 3 Interrupt DMA request 4 Interrupt DMA request 5...

Page 10: ...ication the ECC uses the check bits to automatically correct single bit memory errors Multi bit memory errors are not correctable If the ECC detects a multi bit error an exception is generated The typ...

Page 11: ...et the ERNCR bit in the ECSM Error Configuration Register ECSM_ECR Flash set the EFNCR bit in ECSM_ECR When these bits are set and a non correctable ECC error occurs error information is recorded in o...

Page 12: ...ded Table 10 3 INTC Memory Map Page 10 8 Add the following note at the end of this table Note To ensure compatibility with all PowerPC processors the TLB entry covering the INTC memory map must be con...

Page 13: ...the priority comparator design is that once a higher priority interrupt is captured it must be acknowledged by the CPU before a subsequent interrupt request of even higher priority can be captured Fo...

Page 14: ...rts INTVEC in INTC_IACKR updates with vector for that peripheral interrupt request C ISR108 writes to INTC_CPR to raise priority to 3 before accessing shared coherent data block D PRI in INTC_CPR now...

Page 15: ...L predivider must be configured for divide by two operation by tying PLLCFG 2 low set PREDIV to 0b000 to When using an 8 to 20 MHz reference clock crystal or external clock PLLCFG 2 should be set low...

Page 16: ...d the table shown in EMIOS_CCRn DMA bit description Clarified the description in Section 9 4 1 eDMA Microarchitecture Clarified the description in Section 9 3 1 13 eDMA Interrupt Request Registers EDM...

Page 17: ...se nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation c...

Page 18: ...MPC5565 Microcontroller Reference Manual Devices Supported MPC5565 MPC5565 RM Rev 1 0 09 2007...

Page 19: ...ny such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims co...

Page 20: ...nhanced Time Processing Unit eTPU 1 15 1 4 16 Enhanced Queued A D Converter eQADC 1 16 1 4 17 Deserial Serial Peripheral Interface DSPI 1 16 1 4 18 Enhanced Serial Communications Interface eSCI 1 16 1...

Page 21: ...verview 3 2 3 1 3 Features 3 3 3 1 4 Microarchitecture Summary 3 5 3 2 Core Registers and Programmer s Model 3 6 3 2 1 Power Architecture Registers 3 8 3 2 2 Core Specific Registers 3 11 3 2 3 e200z6...

Page 22: ...External Signal Description 5 3 5 3 Memory Map and Register Definitions 5 4 5 3 1 Register Descriptions 5 5 5 4 Functional Description 5 11 5 4 1 Access Support 5 11 5 4 2 Peripheral Write Buffering...

Page 23: ...ion Status Module ECSM 8 1 Introduction 8 1 8 1 1 Overview 8 1 8 1 2 Features 8 2 8 2 Memory Map and Register Definition 8 2 8 2 1 Register Descriptions 8 3 8 3 Initialization and Application Informat...

Page 24: ...agement 10 24 10 4 3 Details on Handshaking with Processor 10 26 10 5 Initialization Application Information 10 28 10 5 1 Initialization Flow 10 28 10 5 2 Interrupt Exception Handler 10 28 10 5 3 ISR...

Page 25: ...12 4 Functional Description 12 21 12 4 1 External Bus Interface Features 12 21 12 4 2 External Bus Operations 12 26 12 5 Initialization and Application Information 12 61 12 5 1 Booting from External...

Page 26: ...1 Access Timing 14 3 14 6 2 Reset Effects on SRAM Accesses 14 4 14 7 Initialization and Application Information 14 4 14 7 1 Example Code 14 5 14 8 Document Revision History 14 5 Chapter 15 Boot Assist...

Page 27: ...17 1 2 Block Diagram 17 2 17 1 3 eTPU Operation Overview 17 3 17 1 4 eTPU Engine 17 4 17 1 5 Features 17 8 17 2 Modes of Operation 17 10 17 2 1 User Configuration Mode 17 10 17 2 2 User Mode 17 10 17...

Page 28: ...18 95 18 4 7 eQADC eDMA Interrupt Request 18 99 18 4 8 eQADC Synchronous Serial Interface SSI Submodule 18 102 18 4 9 Analog Submodule 18 107 18 5 Initialization Application Information 18 109 18 5 1...

Page 29: ...3 Delay Settings 19 68 19 5 4 MPC5xx QSPI Compatibility with the DSPI 19 68 19 5 5 Calculation of FIFO Pointer Addresses 19 69 19 6 Document Revision History 19 71 Chapter 20 Enhanced Serial Communica...

Page 30: ...4 5 CAN Protocol Related Features 21 29 21 4 6 Modes of Operation Details 21 32 21 4 7 Interrupts 21 33 21 4 8 Bus Interface 21 33 21 5 Initialization and Application Information 21 34 21 5 1 FlexCAN...

Page 31: ...tions 23 8 23 4 5 Boundary Scan 23 10 23 5 Initialization Application Information 23 11 23 6 Document Revision History 23 11 Chapter 24 Nexus Development Interface 24 1 Introduction 24 1 24 1 1 Block...

Page 32: ...chpoint Trigger Register WT 24 43 24 11 7 Data Trace Control Register DTC 24 44 24 11 8 Data Trace Start Address Registers 1 and 2 DTSAn 24 45 24 11 9 Data Trace End Address Registers 1 and 2 DTEAn 24...

Page 33: ...formation 2 4 B 3 1 MPC5565 Calibration Bus Implementation 2 4 B 4 Signals and Pads 2 4 B 4 1 CAL_CS 0 2 3 Calibration Chip Selects 0 2 and 3 2 4 B 4 2 Pad Ring 2 5 B 4 3 CLKOUT 2 5 B 5 Power Supplies...

Page 34: ...MPC5565 Reference Manual Rev 1 0 Freescale Semiconductor 15...

Page 35: ...MPC5565 Reference Manual Rev 1 0 16 Freescale Semiconductor...

Page 36: ...med by an enhanced time processor unit engine eTPU The eTPU engine controls 32 hardware channels The eTPU has been enhanced over the TPU by providing 24 bit timers double action hardware channels a va...

Page 37: ...rval timer GPR General purpose register JTAG JTAG controller LSU Load store unit MMU Memory management unit PCU Program counter unit SPE Signal processing engine SPR Special purpose register TB Time b...

Page 38: ...le slew rate control External bus support 1 62 3 6 V operation and Nexus pins support 2 5 3 6 V operation Selectable drive strength control Unused pins configurable as GPIO Designed with EMI reduction...

Page 39: ...five slave ports 32 bit address bus 64 bit data bus Simultaneous accesses from different masters to different slaves there is no clock penalty when a parked master accesses a slave Enhanced direct mem...

Page 40: ...upport a 32 bit EBI data bus only 16 data bus pins are available and connected on the 324 BGA package The 496 pin VertiCal assembly provides the calibration functionality Memory controller with suppor...

Page 41: ...KB 64 bit configuration Censorship protection scheme to prevent flash content visibility Hardware read while write feature that can erase program blocks while other blocks are read used for EEPROM em...

Page 42: ...k hardware support Shared time or angle counter bus for all eTPU and eMIOS modules DMA and interrupt request support Nexus class 3 debug support with some class 4 support Enhanced queued analog digita...

Page 43: ...receiver LIN support DMA support Interrupt request support Three FlexCANs 64 message buffers each Full implementation of the CAN protocol specification Version 2 0B Based on and including all existin...

Page 44: ...ower the core logic it reduces the number of power supplies required from the customer power supply chip POR block Provides initial reset condition up to the voltage at which pins RESET can be read sa...

Page 45: ...Class 3 Interrupt controller channels 300 231 Analog to digital converter channels 40 40 ADC A Y Y ADC B Y Y Fast Ethernet controller FEC FlexRay FlexRay Nexus data trace Frequency modulated phase loc...

Page 46: ...mize delays during change of flow operations Sequential prefetching is performed to ensure a supply of instructions into the execution pipeline Branch target prefetching is performed to accelerate tak...

Page 47: ...using an additional configuration bit in each table look aside buffer TLB entry in the MMU 1 4 2 System Bus Crossbar Switch XBAR The system bus multi port crossbar XBAR switch supports simultaneous c...

Page 48: ...nterrupt request but then the ISR asserts a software settable interrupt request to finish the servicing in a lower priority ISR 1 4 5 Frequency Modulated Phase Locking Loop FMPLL The frequency modulat...

Page 49: ...system bus port and a 256 bit read data interface to flash memory The FBIU contains two 256 bit prefetch buffers and a prefetch controller that prefetches sequential lines of data from the flash arra...

Page 50: ...e minimum address translation to allow application boot code to execute as either Classic Power Architecture Book E code default or as Freescale VLE code 1 4 14 Enhanced Management Input Output System...

Page 51: ...ry mapped registers The channels and register content are transmitted using a SPI like protocol The MPC5565 has three DSPI modules B C and D The DSPIs have three configurations Serial peripheral inter...

Page 52: ...r JTAGC The JTAG controller JTAGC module provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode Testing is performed via a bou...

Page 53: ...single master mode Using four chip select signals and 26 address bus signals 256 MB can be mapped into the external memory space in single master mode External bus interface 0x4000_0000 Internal SRAM...

Page 54: ...Reserved 0xC3FC_0000 0xC3FC_3FFF 16 KB 3 KB Enhanced time processing unit eTPU registers 0xC3FC_4000 0xC3FC_7FFF 16 KB N A Reserved 0xC3FC_8000 0xC3FC_8BFF 16 KB 2 5 KB eTPU shared data memory paramet...

Page 55: ...0xFFFC_4000 0xFFFC_7FFF 16 KB 1152 Controller area network FlexCAN B 0xFFFC_8000 0xFFFC_BFFF 16 KB 1152 Controller area network FlexCAN C 0xFFFC_C000 0xFFFC_FFFF 16 KB 1152 Reserved 0xFFFD_0000 0xFFF...

Page 56: ...0 0b0100_0000_0000 1 MB Internal SRAM 0x4000_0000 0x4000_FFFF 0b1101 0b0110_0000_0000 1 MB Reserved2 2 Reserved for a future module that requires its own crossbar slave port 0x6000_0000 0x600F_FFFF 0b...

Page 57: ...ed Section 1 2 Features Added page footnote to read Although this device has a maximum of 231interrupts the logic requires that the total number of interrupts be divisible by four Therefore the total...

Page 58: ...e Signals MPC5565 Design 324 Package Maximum 24 bit EBI address bus ADDR 8 31 _GPIO 4 27 ADDR 8 11 are muxed as alternate signals with the chip select signals CS 0 3 _ADDR 8 11 _GPIO 0 3 ADDR 8 11 is...

Page 59: ...IO 103 _PCSC 2 _SINB GPIO 108 _SINC_PCSB 3 GPIO 109 _SCKC_PCSB 4 GPIO 110 _PCSC 0 _PCSB 5 AN 5 _DAN2 AN 6 _DAN3 AN 7 _DAN3 AN 8 _ANW AN 9 _ANX AN 10 _ANY AN 11 _ANZ AN 12 _MA 0 _SDS AN 13 _MA 1 _SDO A...

Page 60: ...available on the device a dash appears in the following Signal table columns Signal Functions P A G and I O Type Figure 2 2 Primary Function Not Available on Device The entries in the P A G column de...

Page 61: ...RSTCFG Up Up P22 Y28 BOOTCFG 0 _ IRQ 2 _ GPIO 211 Boot configuration input External interrupt request GPIO P A G I I I O VDDEH6 SH BOOTCFG Down Down U21 AB26 BOOTCFG 1 _ IRQ 3 _ GPIO 212 Boot configur...

Page 62: ...Up12 AGJ DATA 23 _13 GPIO 51 External data bus 11 GPIO P G I O I O VDDE3 F Up Up12 AH9 DATA 24 _13 GPIO 52 External data bus 11 GPIO P G I O I O VDDE3 F Up Up12 AD7 DATA 25 _13 GPIO 53 External data...

Page 63: ...ion address bus P O VDDE12 F Up Up AA15 CAL_ADDR 15 13 16 Calibration address bus P O VDDE12 F Up Up W7 CAL_ADDR 16 13 16 Calibration address bus P O VDDE12 F Up Up P7 CAL_ADDR 17 13 16 Calibration ad...

Page 64: ...DE7 F O Low Down A17 18 B17 A19 B18 D17 C17 B19 A23 C22 A20 A24 B23 B20 C20 B24 MSEO 1 0 Nexus message start end out P O VDDE7 F O High MSEO High G22 G21 G24 H24 RDY Nexus ready output P O VDDE7 F O H...

Page 65: ...DSPI SCKA_21 PCSC 1 _ GPIO 93 DSPI C peripheral chip select GPIO A G O I O VDDEH6 MH Up Up L22 U27 SINA_21 PCSC 2 _ GPIO 94 DSPI C peripheral chip select GPIO A G O I O VDDEH6 MH Up Up L21 P27 SOUTA_...

Page 66: ...ct GPIO P A G O I O I O VDDEH6 22 MH Up Up L19 M26 eQADC AN 0 _ DAN0 Single ended analog input Positive terminal differential input P I VDDA1 23 AE I AN 0 B8 C9 AN 1 _ DAN0 Single ended analog input N...

Page 67: ...AN 27 28 A12 A13 B12 A13 AN 29 Single ended analog input P I VDDA0 23 AE I AN 29 D13 E13 AN 30 35 Single ended analog input P I VDDA0 23 AE I AN 30 35 C13 B13 B14 C14 D14 A14 C13 B13 B14 E14 G14 A14...

Page 68: ...0 ETPUA 14 _ PCSB 4 _ GPIO 128 eTPU A channel DSPI B peripheral chip select GPIO P A G I O O I O VDDEH1 MH WKPCFG WKPCFG G3 K5 ETPUA 15 _ PCSB 5 _ GPIO 129 eTPU A channel DSPI B peripheral chip select...

Page 69: ...AD21 P21 EMIOS 3 5 _ ETPUA 3 5 _ GPIO 182 184 eMIOS channel eTPU A channel output only GPIO P A G I O O I O VDDEH4 SH WKPCFG WKPCFG AA11 AB12 AA12 R22 AD18 AD22 EMIOS 6 7 _ ETPUA 6 7 _ GPIO 185 186 e...

Page 70: ...Crystal oscillator input External clock input P A I I VDDSYN AE I EXTAL32 U22 AC28 CLKOUT System clock output P O VDDE5 F CLKOUT Enabled CLKOUT Enabled AA20 AF25 ENGCLK Engineering clock output P O VD...

Page 71: ...3 P11 13 R1 V5 AA5 AC1 VDDE3 37 External I O supply input P I 1 8 3 3 V I VDDE3 AB4 AA5 AB5 AB6 AB7 AA7 AA8 AB8 AB9 AA9 Y6 Y7 Y8 W9 W10 Y9 Y10 W11 Y11 T14 U13 14 V12 14 AD9 AD14 AH6 AH14 VDDE5 Externa...

Page 72: ...VDDEH W14 AD20 VDDEH6 External I O supply input P I 3 3 5 0 V I VDDEH U19 V26 VDDEH8 External I O supply input P I 3 3 5 0 V I VDDEH C21 VDDEH9 38 External I O supply input P I 3 3 5 0 V I VDDEH D15...

Page 73: ...sponds to a separate signal function on the pin For all device I O pins the primary alternate or GPIO signal functions are designated in the PA field of the system integration unit SIU PCR registers e...

Page 74: ...AN A pins after execution of the BAM program is determined by the BOOTCFG 0 1 pins Refer to Table 15 9 for details on the FlexCAN pin configurations after the BAM executes 21 The primary signal is not...

Page 75: ...OUT is tri stated 2 3 1 3 Phase Locked Loop Configuration External Interrupt Request GPIO PLLCFG 0 _IRQ 4 _GPIO 208 PLLCFG 0 _IRQ 4 _GPIO 208 are sampled on the negation of the RESET input pin if the...

Page 76: ...ctions are the external interrupt request inputs IRQs 2 3 1 8 Weak Pull Configuration GPIO WKPCFG_GPIO 213 WKPCFG_GPIO 213 determines whether specified eTPU and eMIOS pins are connected to a weak pull...

Page 77: ...signals are not supported in the 324 package 2 3 2 9 External Data GPIO DATA 18 _GPIO 46 DATA 18 _GPIO 46 is an EBI data signal These signals are not supported in the 324 package 2 3 2 10 External Dat...

Page 78: ...GPIO 54 is an EBI data signal These signals are not supported in the 324 package 2 3 2 18 External Data GPIO DATA 27 _GPIO 55 DATA 27 _GPIO 55 is an EBI data signal These signals are not supported in...

Page 79: ...GPIO 68 indicates that the EBI is ready to accept read data 2 3 2 27 External Transfer Start GPIO TS_GPIO 69 TS_GPIO 69 is asserted by the EBI owner to indicate the start of a transfer 2 3 2 28 Extern...

Page 80: ...s timing to a development tool for a single watchpoint or breakpoint occurrence 2 3 3 3 Nexus Message Clock Out MCKO MCKO is a free running clock output to the development tools which is used for timi...

Page 81: ...JTAG Test Clock Input TCK TCK provides the clock input for the on chip test logic 2 3 4 2 JTAG Test Data Input TDI TDI provides the serial test instruction and data input for the on chip test logic 2...

Page 82: ...rnate function is a peripheral chip select output for the DSPI C module 2 3 5 4 FlexCAN B Receive DSPI C Chip Select GPIO CNRXB_PCSC 4 _GPIO 86 CNRXB_PCSC 4 _GPIO 86 is the receive pin for the FlexCan...

Page 83: ...PI A Clock DSPI C Chip Select GPIO SCKA_PCSC 1 _GPIO 93 SCKA_PCSC 1 _GPIO 93 Because the SCKA primary signal function is reserved on this device there is no primary signal function for this ball The a...

Page 84: ...a DSPI clock pin for the DSPI D module 2 3 7 7 DSPI A Chip Select DSPI D Data Input GPIO PCSA 3 _SIND_GPIO 99 PCSA 3 _SIND_GPIO 99 Because the PCSA 3 primary function is reserved on this device there...

Page 85: ...7 14 DSPI B Chip Select DSPI D Chip Select GPIO PCSB 1 _PCSD 0 _GPIO 106 PCSB 1 _PCSD 0 _GPIO 106 PCSB 1 is the primary a peripheral chip select output pin for the DSPI B module The alternate functio...

Page 86: ...AN 1 _DAN0 AN 1 is a single ended analog input to the two on chip ADCs DAN0 is the negative terminal of the differential analog input DAN0 DAN0 to DAN0 2 3 8 3 Analog Input Differential Analog Input...

Page 87: ...Multiplexed Analog Input AN 10 _ANY AN 10 is an analog input pin ANY is an analog input in external multiplexed mode 2 3 8 12 Analog Input Multiplexed Analog Input AN 11 _ANZ AN 11 is an analog input...

Page 88: ...ernal ADCs or used as the multiplexor digital outputs MA 1 This pin is configured by setting the pad configuration register SIU_PCR216 2 3 8 15 Analog Input Mux Address 2 eQADC Serial Data In AN 14 _M...

Page 89: ...rigger for CFIFO1 CFIFO3 and CFIFO5 GPIO 111 112 are general purpose input output functions These signals are not supported in the 324 package 2 3 8 19 Voltage Reference High VRH VRH is the voltage re...

Page 90: ...PIO 116 is an input output channel pin for the eTPU A module ETPUA 2 is the primary functions and is an input output channel for the eTPU A module The alternate function is an output channel for the e...

Page 91: ...he pin functions as output only 2 3 9 11 eTPU A Channel eTPU A Channel Output Only GPIO ETPUA 9 _ETPUA 21 _GPIO 123 ETPUA 9 _ETPUA 21 _GPIO 123 is an input output channel pin for the eTPU A module The...

Page 92: ..._PCSD 1 _GPIO 130 is an input output channel pin for the eTPU A module The alternate function is a peripheral chip select for the DSPI D module 2 3 9 19 eTPU A Channel DSPI D Chip Select GPIO ETPUA 17...

Page 93: ...PIO 138 141 ETPUA 24 27 _IRQ 12 15 _GPIO 138 141 are output channel pins for the eTPU A module The alternate function is external interrupt request inputs for the SIU module 2 3 9 27 eTPU A Channel Ou...

Page 94: ...Data Output GPIO EMIOS 12 _SOUTC_GPIO 191 EMIOS 12 _SOUTC_GPIO 191 is an output channel pin for the eMIOS module The alternate function is the data output for the DSPI C module 2 3 10 4 eMIOS Channel...

Page 95: ...utput channel pin for the eMIOS module 2 3 10 13 eMIOS Channel GPIO EMIOS 23 _GPIO 202 EMIOS 23 _GPIO 202 is an input output channel pin for the eMIOS module 2 3 11 General Purpose Input Output GPIO S...

Page 96: ...ary function and selects the primary chip for calibration It is functional only when using the 496 pin assembly 2 3 12 2 Calibration Chip Select Calibration Address CAL_CS 2 3 _CAL_ADDR 10 11 CAL_CS 2...

Page 97: ...transfer start It is only functional on the 496 assembly 2 3 13 Clock Synthesizer Signals 2 3 13 1 Crystal Oscillator Output XTAL XTAL is the output pin for an external crystal oscillator 2 3 13 2 Cry...

Page 98: ...C 2 3 14 4 eQADC Analog Ground Reference VSSAn VSSAn is the analog ground reference input pin for the eQADC 2 3 14 5 Clock Synthesizer Power Input VDDSYN VDDSYN is the power supply input for the FMPLL...

Page 99: ...ment provides the power and ground for the I O pins and can be powered by any voltage within the allowed voltage range regardless of the power on the other segments The power ground segmentation appli...

Page 100: ...209 PLLCFG 2 RSTCFG_GPIO 210 BOOTCFG 0 _IRQ 2 _GPIO 211 BOOTCFG 1 _IRQ 3 _GPIO 212 WKPCFG_GPIO 213 CNTXC_PCSD 3 _GPIO 87 CNRXC_PCSD 4 _GPIO 88 TXDA_GPIO 89 RXDA_GPIO 90 TXDB_PCSD 1 _GPIO 91 RXDB_PCSD...

Page 101: ...22 125 ETPUA 12 _PCSB 1 _GPIO 126 ETPUA 14 _PCSB 4 _GPIO 128 ETPUA 15 _PCSB 5 _GPIO 129 ETPUA 16 _PCSD 1 _GPIO 130 ETPUA 17 _PCSD 2 _GPIO 131 ETPUA 18 _PCSD 3 _GPIO 132 ETPUA 19 _PCSD 4 _GPIO 133 ETPU...

Page 102: ...5 are connected to the ETPUA 0 3 _ETPUA 12 15 _GPIO 114 117 pins The eTPU TCRA clock input is connected to an external pin only VRC33 3 3 V VRCCTL VFLASH 3 0 3 6 V VPP 4 5 5 25 V2 VSTBY 0 9 1 1 V NC N...

Page 103: ...le 2 5 ETPUA 0 15 DSPI C I O Mapping DSPI C Serialized Input eTPU A Channel Output 15 11 14 10 13 9 12 8 11 7 10 6 9 5 8 4 7 3 6 2 5 1 4 0 3 15 2 14 eTPU A ETPUA 0 _ ETPUA 12 _ GPIO 114 CH0 IN EMIOS 0...

Page 104: ...to DSPI B connections are given in Table 2 6 and ETPU A to DSPI D in Table 2 7 Although not shown in Figure 2 5 the output channels of ETPUA 16 23 are also connected to the ETPUA 4 11 _ETPUA 16 23 _G...

Page 105: ...11 are given in Figure 2 7 Figure 2 8 for EMIOS 12 13 and Figure 2 9 for EMIOS 14 15 8 29 29 7 16 6 17 5 18 4 19 3 20 2 21 1 DSPI B serialized input channels 0 1 14 and 15 are connected to eMIOS chan...

Page 106: ...I O Connections CH11 IN CH11 OUT IN 1 IN 7 DSPI B EMIOS 11 _ GPIO 190 DSPI D IN 0 eMIOS CH10 IN CH10 OUT EMIOS 10 _ GPIO 189 IN 6 CH13 IN CH13 OUT IN 14 IN 9 DSPI B DSPI D OUT 14 eMIOS CH12 IN CH12 O...

Page 107: ...2 4 MPC5565 Power Ground Segmentation for the 496 Assembly Added TXDA and RXDA to CNTXA_GPIO 83 and CNRXA_GPIO 84 signals respectively Added information on the differences between the device design an...

Page 108: ...Power Architecture embedded category The host processor core of the device complies with the Power Architecture embedded category which is 100 percent user mode compatible with the original Power PC u...

Page 109: ...low single cycle branches in many cases The e200z6 core complex is built on a single issue 32 bit Power Architecture design with 64 bit general purpose registers GPRs Power Architecture floating point...

Page 110: ...r reduced code footprint Refer to EREF A Programmer s Reference Manual for Freescale Book E Processors and to VLEPIM Variable Length Encoding VLE Extension Programming Interface Manual In order execut...

Page 111: ...function 32 bit single cycle barrel shifter for static shifts and rotates 32 bit mask unit for data masking and insertion Divider logic for signed and unsigned divides in 6 16 clocks with minimized e...

Page 112: ...st instructions The integer execution unit consists of a 32 bit arithmetic unit AU a logic unit LU a 32 bit barrel shifter shifter a mask insertion unit MIU a condition register manipulation unit CRU...

Page 113: ...multiply divide compare and conversion operations are provided and most operations can be pipelined 3 2 Core Registers and Programmer s Model This section describes the registers implemented in the e...

Page 114: ...BCR2 DBCR31 SPR 308 SPR 309 SPR 310 SPR 561 Instruction Address Compare IAC1 IAC2 IAC3 IAC4 SPR 312 SPR 313 SPR 314 SPR 315 Data Address Compare DAC1 DAC2 SPR 316 SPR 317 1 These e200z6 specific regis...

Page 115: ...te on the entire 64 bit register Condition register CR The 32 bit CR consists of eight 4 bit fields CR0 CR7 that reflect results of certain arithmetic operations and provide a mechanism for testing an...

Page 116: ...er MSR The MSR defines the state of the processor The MSR can be modified by the move to machine state register mtmsr system call sc and return from exception rfi rfci rfdi instructions It can be read...

Page 117: ...s Debug status register DBSR This register contains debug event status Instruction address compare registers IAC1 IAC4 These registers contain addresses and or masks which are used to specify instruct...

Page 118: ...re implementation dependent 1 HID1 controls processor and system functions Exception handling and control registers Debug save and restore registers DSRR0 DSRR1 DSRR0 holds the effective address for t...

Page 119: ...s The e200z6 core complex features that are not supported in the device are described in Table 3 1 Table 3 1 e200z6 Features Not Supported in the Device Core Function Category Description Disabled eve...

Page 120: ...ult constitutes the physical address of the access Table 3 2 shows the TLB entry bit definitions The TLB is accessed indirectly through several MMU assist MAS registers Software can read and write to...

Page 121: ...EPN field and TS a matching TLB entry must match with the current process ID of the access in PID0 or have a TID value of 0 indicating the entry is globally shared among all processes Figure 3 4 show...

Page 122: ...r execute permission Allows instruction fetches to access the page and instructions to be executed from the page while in supervisor mode UR User read permission Allows loads and load type cache manag...

Page 123: ...TLBs The MAS registers can be read or written using the mfspr and mtspr instructions The e200z6 does not implement the MAS5 register present in other Freescale EIS designs because the tlbsx instructio...

Page 124: ...NV W Reset Undefined on Power Up Unchanged on Reset Figure 3 7 MAS Register 0 Format MAS 0 Table 3 3 MAS 0 MMU Read Write and Replacement Control Field Description 0 1 Reserved must be cleared 2 3 TL...

Page 125: ...protected from invalidation 1 Entry is protected from invalidation Protects TLB entry from invalidation by tlbivax TLB1 only or flash invalidates through MMUCSR0 TLB1_FI 2 7 Reserved must be cleared 8...

Page 126: ...th respect to the caches in the system 1 All stores performed to this page are written through to main memory 28 I Cache inhibited 0 This page is considered cacheable 1 This page is considered cache i...

Page 127: ...ss Control Field Description 0 19 RPN Real page number Only bits that correspond to a page number are valid Bits that represent offsets within a page are ignored and must be zero 20 21 Reserved must b...

Page 128: ...Default TSIZE value 24 25 Reserved must be cleared 26 VLED Default VLED value 27 31 DWIMGE Default WIMGE values SPR 630 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 2...

Page 129: ...cted to the cache Addresses from the processor to the cache are virtual addresses used to index the cache array The MMU provides the virtual to physical translation for use in performing the cache tag...

Page 130: ...leword critical doubleword first The line is fetched and placed into the appropriate cache block and the critical doubleword is forwarded to the CPU Subsequent doublewords can be streamed to the CPU i...

Page 131: ...re must invalidate cache before the cache is enabled Figure 3 15 illustrates the general flow of cache operation Figure 3 15 Cache Lookup Flow To determine if the address is already allocated in the c...

Page 132: ...voiding the power associated with reading tag and data information for a disabled way This provides the capability of disabling some ways for instruction accesses and some ways for data accesses to re...

Page 133: ...t 0x0 Figure 3 16 L1 Cache Control and Status Register 0 L1CSR0 Table 3 9 L1CSR0 Field Descriptions Bits Name Description 0 1 WID Way instruction disable 0 The corresponding way is available for repla...

Page 134: ...s in copyback mode When set to writethrough mode the W page attribute from an optional MMU is ignored and all writes are treated as writethrough required When set write accesses are performed in copyb...

Page 135: ...aborted prior to completion This bit is set by hardware on an aborted condition and will remain set until cleared by software writing 0 to this bit location 30 CINV Cache invalidate 0 No cache invali...

Page 136: ...s flushing invalidation by set and way via the L1FINV0 spr 5 6 Reserved read as zeros 7 8 CBSIZE Cache block size 00 The cache implements a block size of 32 bytes 9 10 CREPL Cache replacement policy 1...

Page 137: ...ing point unavailable IVOR 7 SRR 0 1 MSR FP 0 and attempt to execute a Book E floating point operation System call IVOR 8 SRR 0 1 Execution of the system call sc instruction AP unavailable IVOR 9 SRR...

Page 138: ...enated to provide a long period 64 bit counter Debug IVOR 15 DE IDM CSSR 0 1 Debugger when HIDO DAPUEN 0 Caused by trap instruction address compare data address compare instruction complete branch tak...

Page 139: ...s can also be used to perform scalar operations by ignoring the results of the upper 32 bit half of the register file Some instructions are defined that produce a 64 bit scalar result Vector fixed poi...

Page 140: ...ference Manual for Freescale Book E Processors VLEPIM Variable Length Encoding VLE Extension Programming Interface Manual Addendum to e200z6 PowerPCTM Core Reference Manual e200z6 with VLE Errata to e...

Page 141: ...eplaced the following From Undefined on m_por assertion unchanged on p_reset_b assertion To Power Up Unchanged on Reset because m_por and p_reset_b are internal signals In Table 3 1 e200z6 Features No...

Page 142: ...2 2 Reset Output RSTOUT For all reset sources the BOOTCFG 0 1 and PLLCFG 0 1 signals can be used to determine the boot mode and the configuration of the FMPLL respectively If the RSTCFG pin is assert...

Page 143: ...ut RESET The RESET pin is an active low input that is asserted by an external device during a power on or external reset The internal reset signal asserts only if the RESET pin is asserted for 10 cloc...

Page 144: ...4 3 1 Register Descriptions This section describes all the reset controller registers It includes details about the fields in each register the number of bits per field the reset value of the registe...

Page 145: ...BOOTCFG can also be loaded with a default instead of what is on the pin or pins Figure 4 1 Reset Status Register SIU_RSR Table 4 2 SIU_RSR Field Descriptions Field Description 0 PORS Power on reset s...

Page 146: ...was logic 1 and weak pullup is the default setting 17 28 Reserved 29 30 BOOTCFG Reset configuration pin status Holds the value of the BOOTCFG 0 1 pins that was latched four clocks before the last nega...

Page 147: ...rmined number of clock cycles Refer to Section 4 2 2 Reset Output RSTOUT but the MCU is not reset The bit is automatically cleared when the software external reset completes 0 Do not generate an softw...

Page 148: ...ESET pin must be asserted during a power on reset to guarantee proper operation of the MCU The PLLCFG 0 1 and RSTCFG pins determine the configuration of the FMPLL If the RSTCFG pin is asserted at the...

Page 149: ...3 The reset controller then waits four clock cycles before the negating RSTOUT and updating the fields in the SIU_RSR The ERS bit is set and all other reset status bits in the SIU_RSR are cleared Refe...

Page 150: ...s of clock 4 4 2 3 5 Watchdog Timer Debug Reset The WDRS bit in the reset status register SIU_RSR is set when the watchdog timer or a debug request reset occurs A watchdog timer reset occurs and the W...

Page 151: ...the FMPLL is locked the reset controller waits a predetermined number of clock cycles before negating RSTOUT Refer to Section 4 2 2 Reset Output RSTOUT When the clock count finishes the WKPCFG and BO...

Page 152: ...the SIU_SRCR causes the external RSTOUT pin to be asserted for a predetermined number of clocks The SER bit automatically clears after the clock cycle expires A software external reset does not cause...

Page 153: ...KPCFG is latched four clock cycles before RSTOUT negates After reset software can modify the weak pullup down selection for all I O pins through the PCRs in the SIU Refer to Chapter 2 Signal Descripti...

Page 154: ...k E code or as Freescale VLE code and if booting externally sets the bus size Refer to the register indicated in RCHW bit descriptions for a description of each control bit NOTE Do not configure the R...

Page 155: ...RCHW from either 16 or 32 bit external memories Then the BAM reconfigures the EBI either as a 16 bit bus or a 32 bit bus according to the settings of this bit 0 32 bit CS 0 port size 1 16 bit CS 0 po...

Page 156: ...BAM program executes which is for every power on external or internal reset event The only exception to this is the software external reset Refer to Section 4 4 3 5 Reset Configuration Halfword for de...

Page 157: ...G signal is applied at the assertion of the internal reset signal as indicated by the assertion of RSTOUT The values of the WKPCFG and BOOTCFG 0 1 pins are latched 4 clock cycles before the negation o...

Page 158: ...config pins relative to RSTOUT PLLCFG and RSTCFG are 4 clock cycles PLL locked 24001 clock cycles Don t Care and WKPCFG is treated as 1 during POR assertion PLLCFG RSTCFG and WKPCFG are applied but no...

Page 159: ...Flow The following figure shows the process flow used for an external reset Figure 4 5 External Reset Flow Diagram False True RESET asserted Wait 2 clock cycles False True RESET asserted Set latch wa...

Page 160: ...negated Default PLL configuration applied not latched False True Wait 24001 clock cycles Latch WKPCFG pin RSTCFG asserted Latch BOOTCFG values Wait four clock cycles Update reset status register Nega...

Page 161: ...ntegration unit SIU_RSR To determine if WDRS was set by a watchdog timer or debug reset check the WRS field in the e200z6 core TSR The effect of a watchdog timer or debug reset request is the same on...

Page 162: ...functionality is identical The only difference is the peripherals to which they connect Accesses that fall within the address space of the PBRIDGE are decoded to provide individual module selects for...

Page 163: ...st of master slave IDs and the peripherals for with each master and slave Refer to Section 13 3 2 9 Flash Bus Interface Unit Access Protection Register FLASH_BIUAPR for more information on access prot...

Page 164: ...rted to each slave peripheral Supports a pair of slave accesses for 64 bit instruction fetches Provides configurable per module write buffering support Provides configurable per module and per master...

Page 165: ...m peripheral access control register 1 32 Base 0x0048 PBRIDGE_A_OPACR2 Off platform peripheral access control register 2 32 Base 0x004C Base 0x0053 Reserved Table 5 3 PBRIDGE B Memory Map Address Regi...

Page 166: ...ess Base 0x0000 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R MBW 0 MTR 0 MTW 0 MPL 0 MBW 1 MTR 1 MTW 1 MPL 1 MBW 2 MTR 2 MTW 2 MPL 2 MBW 3 MTR 3 MTW 3 MPL 3 W Reset 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1...

Page 167: ...ffer writes from the eDMA Writes not able to be buffered by default 0 Write accesses from the eDMA are not bufferable 1 Write accesses from the eDMA are allowed to be buffered 9 MTR2 Master trusted fo...

Page 168: ...access levels supported by the given module Each OPACR contains up to eight of these module access fields and the OPACR register structure is shown in Table 5 2 and Table 5 3 The OPACR registers with...

Page 169: ...0 0 0 0 0 0 0 0 0 Reset B_PACR2 0 12 0 0 0 12 0 0 0 12 0 0 0 12 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R BW4 SP4 WP4 TP4 BW5 SP5 WP5 TP5 BW6 SP6 WP6 TP6 BW7 SP7 WP7 TP7 W Reset A_PACR0 0...

Page 170: ...bit is not writeable 1 5 9 13 17 21 25 29 SPn Supervisor protect Determines whether the peripheral requires supervisor privilege level for access Supervisor privilege level required by default 0 This...

Page 171: ...R Access Control Registers and Peripheral Mapping Register Register Address Peripheral Access Field Peripheral Type Access Field Default Value PBRIDGE A PBRIDGE_A_PACR0 PBRIDGE_A_Base 0x0020 0 PBRIDGE...

Page 172: ...ough no explicit checking is performed by the PBRIDGE NOTE Data accesses that cross a 32 bit boundary are not supported 5 4 2 Peripheral Write Buffering The PBRIDGE provides programmable write bufferi...

Page 173: ...t least the number of system clock cycles that the actual write is delayed Refer to Section 10 4 3 1 2 End of Interrupt Exception Handler 5 4 2 1 Read Cycles Read accesses are possible with the PBRIDG...

Page 174: ...are located on 16 KB boundaries Each slave peripheral is allocated one 16 KB block of the memory map and is activated by one of the module enables from the PBRIDGE Up to thirty two 16 KB external sla...

Page 175: ...owing write accesses to be terminated on the system bus in a single clock cycle and then subsequently performed on the slave interface Write buffering is controllable on a per peripheral basis The PBR...

Page 176: ...tegration Unit SIU 6 1 Introduction This chapter describes the device system integration unit SIU that configures and initializes the following controls MCU reset configuration System reset operation...

Page 177: ...rossbar switch Figure 6 1 SIU Block Diagram NOTE The power on reset detection module pad interface pad ring module and peripheral I O channels are external to the SIU Reset RESET configuration SIU reg...

Page 178: ...from the set of multiplexed functions Pullup down characteristics of the pin Slew rate for slow and medium pads Open drain mode for output pins Hysteresis for input pins Drive strength of bus signals...

Page 179: ...I O Type Pad Type Pullup Pulldown1 1 Internal weak pullup down The reset weak pullup down state is given by the pullup down state for the primary signal function For example the reset weak pullup down...

Page 180: ...bit general purpose data input SIU_GPDIn and a general purpose data output SIU_GPDOn register Refer to the following sections for more information Section 6 3 1 151 GPIO Pin Data Output Registers 0 2...

Page 181: ...led by setting a bit in IRQ rising edge event enable register SIU_IREER IRQ falling edge event enable register SIU_IFEER If the bit is set in both registers both rising and falling edge events trigger...

Page 182: ...ER SIU_IFEER IRQ flag bit is set in the external interrupt status register SIU_EISR Enable bit is cleared in the DMA interrupt request enable register SIU_DIRER Select bit is cleared in the DMA interr...

Page 183: ...ions for more information Section 6 3 1 4 External Interrupt Status Register SIU_EISR Section 6 3 1 7 Overrun Status Register SIU_OSR Section 6 3 1 8 Overrun Request Enable Register SIU_ORER 6 2 1 6 4...

Page 184: ...RQ rising edge event enable register 32 Base 0x002C SIU_IFEER IRQ falling edge event enable register 32 Base 0x0030 SIU_IDFR IRQ digital filter register 32 Base 0x0034 Base 0x003F Reserved Base 0x0040...

Page 185: ...is mask programmed with the specific mask revision level of the device The current value applies to revision 0 and is updated for each mask revision The MCU ID register is 32 bits Figure 6 2 shows th...

Page 186: ...et requests of different priorities occur on the same clock cycle the reset request with the highest priority is serviced and only that reset request s status bit is set Table 6 6 SIU_MIDR Field Descr...

Page 187: ...ister receives the reset values during power on reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R WKP CFG2 2 The reset value of the WKPCFG bit is the value on the...

Page 188: ...t reset source acknowledged by the reset controller was not an enabled checkstop reset 1 The last reset source acknowledged by the reset controller was an enabled checkstop reset 6 13 Reserved 14 SSRS...

Page 189: ...ise if the RSTCFG pin was negated at the last negation of RSTOUT and the lower half of the censorship control word does not equal 0xFFFF or 0x0000 then the BOOTCFG field is set to the value 0b00 Refer...

Page 190: ...same clock cycle with no reset request by a higher priority reset source therefore the status bits for all the requesting resets are set Refer to Table 6 7 Address Base 0x0010 Access R W 0 1 2 3 4 5 6...

Page 191: ...er reset source asserts 0 No software system reset 1 Generate an software internal system reset 1 SER Software external reset Used to generate a software external reset Writing a 1 to this bit asserts...

Page 192: ...9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R EIF15 EIF14 EIF13 EIF12 EIF11 EIF10 EIF9 EIF8 EIF7 EIF6...

Page 193: ...the assertion of the interrupt request from the SIU to the interrupt controller when an edge triggered event occurs on the IRQ n pin 0 External interrupt request is disabled 1 External interrupt requ...

Page 194: ...2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R OVF15 OVF14 OVF13 OVF12 OVF11 OVF10 OVF9...

Page 195: ...e fields in the overrun request enable register Address Base 0x0024 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18...

Page 196: ...SIU_IFEER Address Base 0x0028 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31...

Page 197: ...lling edge event enable n Enables falling edge triggered events on the corresponding IRQ n pin 0 Falling edge event is disabled 1 Falling edge event is enabled Address Base 0x0030 Access R W 0 1 2 3 4...

Page 198: ...h the primary function followed by the alternate function and then GPIO In some cases the third function can be a secondary alternate which supersedes the GPIO Those exceptions are noted in the docume...

Page 199: ...ls the pad drive strength Drive strength control pertains to pins with the fast I O pad type 00 10 pF drive strength 01 20 pF drive strength 10 30 pF drive strength 11 50 pF drive strength 10 ODE Open...

Page 200: ...device for the pad 15 WPS Weak pullup down select Controls whether weak pullup or weak pulldown devices are used for the pad when weak pullup down devices are enabled The WKPCFG pin determines whether...

Page 201: ...0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA1 1 Do not configure the PA fields in PCR1 3 and PCR5 7 to select ADDR 9 11 Configure only one set of pins to ADDR 9 11 for the address input OBE2 2 W...

Page 202: ...IBE3 3 When configured as ADDR 8 11 or GPDO set the IBE bit to 1 to reflect the pin state in the GPDI register Clear the IBE bit to 0 to reduce power consumption When configured as GPDI set the IBE bi...

Page 203: ...Pin Function 0b0 GPIO 8 22 0b1 ADDR 12 26 Address Base 0x006E through Base 0x0072 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 PA OBE1 1 When configured as ADDR 27 29 the OBE bit has n...

Page 204: ...1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 PA OBE1 1 When configured as ADDR 30 31 the OBE bit has no effect When configured as GPDO set the OBE bit to 1 IBE2 2 When configured as ADDR 30 31 or G...

Page 205: ...t the pin state in the GPDI register Clear the IBE to 0 to reduce power consumption When configured as GPDI set the IBE bit to 1 DSC ODE3 3 When configured as DATA 0 15 clear the ODE bit to 0 HYS4 4 I...

Page 206: ...r the IBE bit to 0 to reduce power consumption When configured as GPDI set the IBE bit to 1 DSC ODE3 3 When configured as DATA 21 the ODE bit should be set to 0 HYS4 4 If external master operation is...

Page 207: ...Invalid value 0b11 DATA 21 Address Base 0x00A6 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA OBE1 1 When configured as DATA 23 the OBE bit has no effect When configured as GPDO set the...

Page 208: ...e IBE bit to 0 to reduce power consumption When configured as GPDI set the IBE bit to 1 DSC ODE3 3 When configured as DATA 24 clear the ODE bit to 0 HYS4 4 If external master operation is enabled clea...

Page 209: ...10 Invalid value 0b11 DATA 25 Address Base 0x00AC Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA OBE1 1 When configured as DATA 26 the OBE bit has no effect When configured as GPDO set...

Page 210: ...er Clear the IBE bit to 0 to reduce power consumption When configured as GPDI set the IBE bit to 1 DSC ODE3 3 When configured as DATA 27 clear the ODE bit to 0 HYS4 4 If external master operation is e...

Page 211: ...b10 Invalid value 0b11 DATA 28 Address Base 0x00B2 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA OBE1 1 When configured as DATA 29 the OBE bit has no effect When configured as GPDO set...

Page 212: ...r Clear the IBE bit to 0 to reduce power consumption When configured as GPDI set the IBE bit to 1 DSC ODE3 3 When configured as DATA 30 clear the ODE bit to 0 HYS4 4 If external master operation is en...

Page 213: ...BE1 1 When configured as RD_WR the OBE bit has no effect When configured as GPDO set the OBE bit to 1 IBE2 2 When the pad is configured as an output set the IBE bit to 1 to show the pin state in the G...

Page 214: ..._GPIO 66 67 Address Base 0x00C0 through Base 0x00C2 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 PA OBE1 1 When configured as WE BE 0 1 the OBE bit has no effect When configured as GPD...

Page 215: ...n the pad is configured as an output set the IBE bit to 1 to show the pin state in the GPDI register Clear the IBE bit to 0 to reduce power consumption When configured as GPDI set the IBE bit to 1 DSC...

Page 216: ...the IBE bit to 0 to reduce power consumption When configured as GPDI set the IBE bit to 1 DSC ODE3 3 When configured as TA and external master operation is enabled clear the ODE bit to 0 HYS4 4 When...

Page 217: ...is disabled in the device OBE2 2 When configured as GPDO set the OBE bit to 1 IBE3 3 When the pad is configured as an output set the IBE bit to 1 to show the pin state in the GPDI register Clear the...

Page 218: ...unction direction and electrical attributes of CNTXA_TXDA_GPIO 83 Figure 6 44 CNTXA_TXDA_GPIO 83 Pad Configuration Register SIU_PCR83 Refer to Table 6 19 for bit field definitions Table 6 41 lists the...

Page 219: ...11 12 13 14 15 R 0 0 0 0 PA OBE1 1 When configured as CNRXA or RXDA the OBE bit has no effect When configured as GPDO set the OBE bit to 1 IBE2 2 When the pad is configured as an output set the IBE bi...

Page 220: ...nitions Table 6 44 lists the PA fields for CNRXB_PCSC 4 _GPIO 86 Table 6 43 PCR85 PA Field Definition PA Field Pin Function 0b00 GPIO 85 0b01 CNTXB 0b10 PCSC 3 0b11 CNTXB Address Base 0x00EC Access R...

Page 221: ...When configured as CNTXC or PCSD 3 the OBE bit has no effect When configured as GPDO set the OBE bit to 1 IBE2 2 When the pad is configured as an output set the IBE bit to 1 to show the pin state in...

Page 222: ...s Base 0x00F2 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 PA OBE1 1 When configured as TXDA the OBE bit has no effect When configured as GPDO set the OBE bit to 1 IBE2 2 When the pad...

Page 223: ...d as TXDB or PCSD 1 the OBE bit has no effect When configured as GPDO set the OBE bit to 1 IBE2 2 When the pad is configured as an output set the IBE bit to 1 to show the pin state in the GPDI registe...

Page 224: ..._GPIO 93 Table 6 48 PCR92 PA Field Definition PA Field Pin Function 0b00 GPIO 92 0b01 RXDB 0b10 PCSD 5 0b11 RXDB Address Base 0x00FA Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA1 1 T...

Page 225: ...the device Do not select 0b01 or 0b11 for the PA field OBE2 2 When configured as PCSC 2 the OBE bit has no effect When configured as GPDO set the OBE bit to 1 IBE3 3 When the pad is configured as an...

Page 226: ...GPIO 96 Table 6 51 PCR95 PA Field Definition PA Field Pin Function 0b00 GPIO 95 0b01 Invalid value 0b10 PCSC 5 0b11 Invalid value Address Base 0x0100 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R...

Page 227: ...ilable on the device Do not select 0b01 or 0b11 for the PA field OBE2 2 When configured as PCSB 2 the OBE bit has no effect When configured as GPDO set the OBE bit to 1 IBE3 3 When the pad is configur...

Page 228: ...O 99 Table 6 54 PCR98 PA Field Definition PA Field Pin Function 0b00 GPIO 98 0b01 Invalid value 0b10 SCKD 0b11 Invalid value Address Base 0x0106 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0...

Page 229: ...elect 0b01 or 0b11 for the PA field OBE2 2 When configured as SOUTD the OBE bit has no effect When configured as GPDO set the OBE to 1 IBE3 3 When SOUTD is configured for slave operation set the IBE b...

Page 230: ...or SCKB_PCSC 1 _GPIO 102 Table 6 57 PCR101 PA Field Definition PA Field Pin Function 0b00 GPIO 101 0b01 Invalid value 0b10 PCSB 3 0b11 Invalid value Address Base 0x010C Access R W 0 1 2 3 4 5 6 7 8 9...

Page 231: ...ed as SINB clear the OBE bit to 0 When configured as PCSC 2 the OBE bit has no effect When configured as GPDO set the OBE bit to 1 IBE2 2 When the pad is configured as an output set the IBE bit to 1 t...

Page 232: ...d Pin Function 0b00 GPIO 104 0b01 SOUTB 0b10 PCSC 5 0b11 SOUTB Address Base 0x0112 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA OBE1 1 When configured as PCSB 0 set the OBE bit to 1 f...

Page 233: ...clear to 0 for slave operation When configured as PCSB 1 the OBE bit has no effect When configured as GPDO set the OBE bit to 1 IBE2 2 When configured as PCSD 0 in slave operation set the IBE bit to 1...

Page 234: ...elds for PCSB 3 _SINC_GPIO 108 Table 6 63 PCR107 PA Field Definition PA Field Pin Function 0b00 GPIO 107 0b01 PCSB 2 0b10 SOUTC 0b11 PCSB 2 Address Base 0x0118 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12...

Page 235: ...red as GPDO set the OBE bit to 1 IBE2 2 When the pad is configured as an output set the IBE bit to 1 to show the pin state in the GPDI register Clear the IBE bit to 0 to reduce power consumption When...

Page 236: ...ds for ETRIG 0 1 _GPIO 111 112 Table 6 66 PCR110 PA Field Definition PA Field Pin Function 0b00 GPIO 110 0b01 PCSB 5 0b10 PCSC 0 0b11 PCSB 5 Address Base 0x011E through Base 0x0120 Access R W 0 1 2 3...

Page 237: ...15 R 0 0 0 0 PA OBE1 1 When configured as TCRCLKA or IRQ 7 the OBE bit has no effect When configured as GPDO set the OBE bit to 1 IBE2 2 When the pad is configured as an output set the IBE bit to 1 t...

Page 238: ...A 16 _GPIO 118 Table 6 69 PCR114 PCR117 PA Field Definition PA Field Pin Function 0b00 GPIO 114 117 0b01 ETPUA 0 3 0b10 ETPUA 12 15 0b11 ETPUA 0 3 Address Base 0x012C Access R W 0 1 2 3 4 5 6 7 8 9 10...

Page 239: ...0 PA OBE1 1 When ETPUA 5 or GPIO 119 are configured as outputs set the OBE bit to 1 When configured as ETPUA 17 the OBE bit has no effect IBE2 2 The IBE bit must be set to one for ETPUA 5 ETPUA 17 an...

Page 240: ...lds for ETPUA 7 _ETPUA 19 _GPIO 121 Table 6 72 PCR120 PA Field Definition PA Field Pin Function 0b00 GPIO 120 0b01 ETPUA 6 0b10 ETPUA 18 0b11 ETPUA 6 Address Base 0x0132 Access R W 0 1 2 3 4 5 6 7 8 9...

Page 241: ...14 15 R 0 0 0 0 PA OBE1 1 The OBE bit must be set to 1 for ETPUA 8 10 or GPIO 122 124 when configured as outputs When configured as ETPUA 20 the OBE bit has no effect IBE2 2 The IBE bit must be set t...

Page 242: ...d Definition PA Field Pin Function 0b00 GPIO 125 0b01 ETPUA 11 0b10 ETPUA 23 0b11 ETPUA 11 Address Base 0x013C Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA OBE1 1 When configured as P...

Page 243: ...bit must be set to 1 for ETPUA 13 15 or GPIO 127 129 when configured as outputs IBE2 2 The IBE bit must be set to 1 for ETPUA 13 15 PSCB 3 5 or GPIO 127 129 when configured as inputs When configured...

Page 244: ...R130 133 PA Field Definition PA Field Pin Function 0b00 GPIO 130 133 0b01 ETPUA 16 19 0b10 PCSD 1 4 0b11 ETPUA 16 19 Address Base 0x014C Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA O...

Page 245: ...ed as outputs IBE2 2 When the pad is configured as an output setting the IBE bit to 1 allows the pin state to be reflected in the corresponding GPDI register Setting the IBE bit to zero reduces power...

Page 246: ...36 PA Field Definition PA Field Pin Function 0b00 GPIO 136 0b01 ETPUA 22 0b10 IRQ 10 0b11 ETPUA 22 Address Base 0x0152 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA OBE1 1 When configu...

Page 247: ...as ETPUA 24 27 or IRQ 12 15 the OBE bit has no effect The OBE bit must be set to 1 for GPIO 138 141 when configured as output IBE2 2 When the pad is configured as an output set the IBE bit to 1 to sh...

Page 248: ...n this device Table 6 84 PCR142 144 PA Field Definition PA Field Pin Function 0b00 GPIO 142 144 0b01 ETPUA 28 30 0b10 PCSC 1 3 0b11 ETPUA 28 30 Address Base 0x0160 through Base 0x0162 Access R W 0 1 2...

Page 249: ...12 13 14 15 R 0 0 0 0 PA OBE1 1 The OBE bit must be set to 1 for EMIOS 0 9 or GPIO 179 188 when configured as output IBE2 2 When the pad is configured as an output set the IBE bit to 1 to show the pi...

Page 250: ...12 _SOUTC_GPIO 191 Table 6 87 PCR189 190 PA Field Definition Pin Function GPIO 189 190 EMIOS 10 11 PCSD 3 4 EMIOS 10 11 Address Base 0x01BE Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0...

Page 251: ...to 1 for GPIO 192 when configured as an output IBE2 2 When the pad is configured as an output set the IBE bit to 1 to show the pin state in the GPDI register Clear the IBE bit to 0 to reduce power con...

Page 252: ..._GPIO 194 Table 6 90 PCR193 PA Field Definition PA Field Pin Function 0b00 GPIO 193 0b01 EMIOS 14 0b10 IRQ 0 0b11 EMIOS 14 Address Base 0x01C2 through Base 0x01C8 Access R W 0 1 2 3 4 5 6 7 8 9 10 11...

Page 253: ...when configured as output IBE3 3 When the pad is configured as an output set the IBE bit to 1 to show the pin state in the GPDI register Clear the IBE bit to 0 to reduce power consumption The IBE bit...

Page 254: ...nction 0b00 GPIO 196 0b01 EMIOS 17 0b10 Invalid value 0b11 EMIOS 17 Address Base 0x01C6 through Base 0x01CC Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA1 1 The PA function using the 0...

Page 255: ...e set to 1 for EMIOS 19 and GPIO 198 when configured as output IBE3 3 When the pad is configured as an output set the IBE bit to 1 to show the pin state in the GPDI register Clear the IBE bit to 0 to...

Page 256: ...ield Pin Function 0b00 GPIO 199 200 0b01 EMIOS 20 21 0b10 Invalid value 0b11 EMIOS 20 21 Address Base 0x01D2 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA1 1 The PA function using the...

Page 257: ...x01D4 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA1 1 The PA function using the 0b10 value is disabled on this device OBE2 2 The OBE bit must be set to 1 for EMIOS 23 or GPIO 202 when...

Page 258: ...These registers are separate from the PCR for GPIO 205 since GPIO 206 207 are fast pad types with drive strength control and GPIO 205 is a medium pad type with slew rate control The PA bit is not impl...

Page 259: ...et the IBE bit to 1 to show the pin state in the GPDI register When configured as GPDI set the IBE bit to 1 DSC ODE HYS 0 0 WPE WPS W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Address Base 0x01E0 Access R...

Page 260: ...PA field to 0b010 for IRQ 5 0b100 for SOUTD and 0b000 for GPIO 209 OBE2 2 When configured as IRQ 5 the OBE bit has no effect When configured as GPDO set the OBE bit to 1 IBE3 3 When the pad is config...

Page 261: ...asserted during reset Set the PA field to 0b10 for IRQ 2 3 or to 0b00 for GPIO 211 212 OBE2 2 When configured as IRQ 2 3 the OBE bit has no effect When configured as GPDO set the OBE bit to 1 IBE3 3...

Page 262: ...S Pad Configuration Register SIU_PCR215 Refer to Table 6 19 for bit field definitions Table 6 103 lists the PA fields for AN 12 _MA 0 _SDS Address Base 0x01EC Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 1...

Page 263: ...uffers are enabled disabled based on PA selection Both input and output buffers are disabled for AN 13 function Output buffers only can be enabled for MA 1 and SDO functions 2 To select the SDO functi...

Page 264: ...gth of MDO 3 0 Figure 6 118 MDO 3 0 Pad Configuration Register SIU_PCR223 SIU_PCR220 Address Base 0x01F4 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA1 2 1 Input and output buffers are...

Page 265: ...121 EVTO Pad Configuration Register SIU_PCR227 6 3 1 124 Pad Configuration Register 228 SIU_PCR228 The SIU_PCR228 register controls the drive strength of TDO Figure 6 122 TDO Pad Configuration Regist...

Page 266: ...isters are not implemented in this device 6 3 1 128 Pad Configuration Register 256 SIU_PCR256 The SIU_PCR256 register controls the function direction and electrical attributes of CAL_CS 0 Figure 6 125...

Page 267: ...on direction and electrical attributes of CAL_ADDR 12 Figure 6 127 CAL_ADDR 12 Pad Configuration Register SIU_PCR259 Refer to Table 6 19 for bit field definitions Table 6 109 lists the PA fields for C...

Page 268: ...tes of CAL_ADDR 14 Figure 6 129 CAL_ADDR 14 Pad Configuration Register SIU_PCR261 Refer to Table 6 19 for bit field definitions Table 6 111 lists the PA fields for CAL_ADDR 14 Address Base 0x0248 Acce...

Page 269: ...gister 264 SIU_PCR264 The SIU_PCR264 register controls the function direction and electrical attributes of CAL_ADDR 17 Figure 6 131 CAL_ADDR 17 Pad Configuration Register SIU_PCR264 Address Base 0x024...

Page 270: ...266 SIU_PCR266 The SIU_PCR266 register controls the function direction and electrical attributes of CAL_ADDR 19 Figure 6 133 CAL_ADDR 19 Pad Configuration Register SIU_PCR266 Table 6 114 PCR264 PA Fi...

Page 271: ...Figure 6 135 CAL_ADDR 21 Pad Configuration Register SIU_PCR268 Refer to Table 6 19 for bit field definitions Table 6 118 lists the PA fields for CAL_ADDR 21 Table 6 116 PCR266 PA Field Definition PA F...

Page 272: ...DDR 23 24 Figure 6 137 CAL_ADDR 23 24 Pad Configuration Registers SIU_PCR270 SIU_PCR271 Refer to Table 6 19 for bit field definitions Table 6 120 lists the PA fields for CAL_ADDR 23 24 Address Base 0x...

Page 273: ...l attributes of CAL_ADDR 28 Figure 6 139 CAL_ADDR 28 Pad Configuration Registers SIU_PCR275 Refer to Table 6 19 for bit field definitions Table 6 122 lists the PA fields for CAL_ADDR 28 Address Base 0...

Page 274: ...egisters SIU_PCR277 Refer to Table 6 19 for bit field definitions Table 6 124 lists the PA fields for CAL_ADDR 30 6 3 1 146 Pad Configuration Register 278 293 SIU_PCR278 SIU_PCR293 The SIU_PCR278 293...

Page 275: ...The SIU_PCR295 SIU_PCR296 registers control the function direction and electrical attributes of CAL_WE BE 0 1 Figure 6 144 CAL_WE BE 0 1 Pad Configuration Registers SIU_PCR295 296 Address Base 0x026C...

Page 276: ...le 6 129 lists the PA fields for CAL_TS 6 3 1 151 GPIO Pin Data Output Registers 0 213 SIU_GPDOn The 8 bit SIU_GPDOn registers defined in Figure 6 147 each specify the output data for the function ass...

Page 277: ...n registers defined in Figure 6 148 each specify the input state for the function assigned to the GPDI n pin The n notation in the 178 SIU_GPDIn register names relate to the n in GPIO n signal name Fo...

Page 278: ...ADC the timer output pin must change to the state that the eQADC recognizes as a trigger Bear in mind there are rising or falling edges and low or high gated trigger types so it might be possible to h...

Page 279: ...le 6 133 SIU_ETISR Field Descriptions Bits Name Description 0 1 TSEL5 0 1 eQADC trigger input select 5 Specifies the input for eQADC trigger 5 00 GPIO 207 01 ETPUA 26 channel 10 EMIOS 12 channel 11 ET...

Page 280: ...0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R ESEL7 ESEL6 ESEL5 ESEL4 ESEL3 ESEL2 ESEL1 ESEL0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 6 134 SIU_EIISR Field Descriptions...

Page 281: ...11 serialized input ETPUA 28 14 15 ESEL8 0 1 External IRQ input select 8 Specifies the input for IRQ 8 00 IRQ 8 01 PCSB 8 serialized input ETPUA 29 10 PCSC 9 serialized input ETPUA 5 11 PCSD 10 serial...

Page 282: ...ies the input for IRQ 2 00 IRQ 2 01 PCSB 2 serialized input ETPUA 21 10 PCSC 3 serialized input ETPUA 15 11 PCSD 4 serialized input ETPUA 17 28 29 ESEL1 0 1 External IRQ input select 1 Specifies the i...

Page 283: ...10 SCKC Master 11 SCKD Master 14 15 TRIGSELB 0 1 DSPI B trigger input select Specifies the source of the PCSB trigger input for master or slave mode 00 Invalid value 01 Invalid value 10 PCSC 4 11 PCS...

Page 284: ...ue 10 PCSB 0 master 11 PCSC 0 master 28 29 SCKSELD 0 1 DSPI D clock input select Specifies the source of the PCSD clock input in slave mode 00 PCSA 2 _SCKD_GPIO 98 pin 01 Invalid value 10 SCKB master...

Page 285: ...d 1 Nexus disable input signal is asserted 16 29 Reserved 30 CSRE The CRSE bit enables the suppression of reflection from the EBI s calibration bus onto the non calibration bus The EBI drives some out...

Page 286: ...cifies the frequency ratio between the system clock and ENGCLK The ENGCLK frequency is divided from the system clock frequency according to the following equation The maximum ENGCLK frequency is 66 MH...

Page 287: ...result appears in the MATCH bit in the SIU_CCR register The SIU_CARH holds the 32 bit value that is compared against the value in the SIU_CBRH register The CMPAH field is read write and is reset by t...

Page 288: ...CBRH holds the 32 bit value that is compared against the value in the SIU_CARH The CMPBH field is read write and is reset by the synchronous reset signal Figure 6 156 Compare B Register High SIU_CBRH...

Page 289: ...to initiate a FlexCAN or eSCI boot Table 6 138 defines the boot modes specified by the BOOTCFG 0 1 pins If the RSTCFG pin is asserted during the assertion of RSTOUT except in the case of a software e...

Page 290: ...reset controller detects that the RESET pin is asserted for more than two clock cycles the event is latched After the latch is set if the RESET pin is negated before 10 clock cycles is reached the res...

Page 291: ...IO Operation All GPIO functions for the device are provided by the SIU Each device pad that has a GPIO signal has a pin configuration register PCR in the SIU where the GPIO function is selected In add...

Page 292: ...trigger is configured in the eQADC trigger input select register SIU_ETISR As shown in the figure the ETRIG 0 input of the eQADC can be connected to either the ETRIG 0 _GPIO 111 pin the ETPUA 30 chann...

Page 293: ...s given in Figure 6 161 Figure 6 161 DSPI Serialized Input Multiplexing 6 4 5 3 Multiplexed Inputs for DSPI Multiple Transfer Operation Each DSPI module can be combined in a serial or parallel chain m...

Page 294: ...CK IN and trigger signals of each DSPI The input source for the SIN input of a DSPI can be a pin or the SOUT of any of the other three DSPIs The input source for the SS input of a DSPI can be a pin or...

Page 295: ...n the Reset Output RSTOUT signal description to read During an internal power on reset POR RSTOUT is tri stated Changes to table 6 6 SIU_MIDR Field Descriptions Removed reference to the Signals chapte...

Page 296: ...CSP low 110 Selects the 496 Calibration assembly set CSP high 111 Reserved Changed the footnote in the RESET status SIU_RSR register to emphasize the fact that any reset and not just a power on reset...

Page 297: ...PIO 111 112 Pad Configuration Register SIU_PCR112 SIU_PCR112 Removed When ETRIG 0 1 is configured the OBE has no effect from footnote 2 Section 6 3 1 44 Pad Configuration Register 82 75 SIU_PCR82 SIU_...

Page 298: ...Diagram Figure 7 1 shows a block diagram of the crossbar switch Figure 7 1 XBAR Block Diagram Table 7 1 gives the crossbar switch port for each master and slave and the assigned and fixed ID number f...

Page 299: ...equal priority and are granted access to a slave port in round robin fashion based upon the ID of the last master to be granted access A block diagram of the XBAR is shown in Figure 7 1 The XBAR can p...

Page 300: ...Base 0x000F Reserved Base 0x0010 XBAR_SGPCR0 General purpose control register for slave port 0 32 Base 0x0014 Base 0x00FF Reserved Base 0x0100 XBAR_MPR1 Master priority register for slave port 1 32 Ba...

Page 301: ...Registers XBAR_MPRn The XBAR_MPR for a slave port sets the priority of each master port when operating in fixed priority mode They are ignored in round robin priority mode unless more than one master...

Page 302: ...18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 MSTR3 not used 0 MSTR2 0 MSTR1 0 MSTR0 W Reset 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 Figure 7 2 Master Priority Registers XBAR_MPRn Table 7 4 XBAR_MPRn Descript...

Page 303: ...ave not being accessed by another master because it is not parked on any master The XBAR_SGPCR can only be accessed in supervisor mode with 32 bit accesses After the RO read only bit is set in the XBA...

Page 304: ...lave port s registers can be written 1 All this slave port s registers are read only and cannot be written attempted writes have no effect and result in an error response 1 21 Reserved must be cleared...

Page 305: ...questing master receives wait states until the targeted slave port can service the master request The latency in servicing the request depends on each master s priority level and the responding slave...

Page 306: ...the XBAR is completely transparent and the master access is immediately transmitted on the slave bus and no arbitration delays are incurred A master access stall if the access decodes to a slave port...

Page 307: ...e that the proper master if any has control of the slave port If the new requesting master s priority level is higher than that of the master that currently has control of the slave port the higher pr...

Page 308: ...questing master must wait until the end of the fixed length burst transfer before it is granted control of the slave port If the new requesting master s priority level is lower than that of the master...

Page 309: ...t and Master ID as shown in Table 7 3 Changed wording of reserved fields in registers From Reserved To Reserved must be cleared Table 7 4 XBAR_MPRn Descriptions Added text for MPR3 and MPR6 fields tha...

Page 310: ...rors correctable and non correctable A correctable ECC error is generated when only one bit is wrong in a 64 bit doubleword In this case it is corrected automatically by hardware and no flags or other...

Page 311: ...8 Base 0x001A Reserved Base 0x001B ECSM_SWTSR Software watchdog timer service register1 8 Base 0x001C Base 0x001E Reserved Base 0x001F ECSM_SWTIR Software watchdog timer interrupt register1 8 Base 0x0...

Page 312: ...nded The values in these registers should be left in their reset state Any change from reset values may cause an unintentional ECSM_SWTIR_SWTIC interrupt 8 2 1 2 ECC Registers There are a number of pr...

Page 313: ...enabled ECC event If there is a pending ECC interrupt and another properly enabled ECC event occurs the ECSM hardware automatically handles the ECSM_ESR reporting clearing the previous data and loadin...

Page 314: ...generate ECC events double bit noncorrectable errors that are terminated with an error response If an attempt to force a non correctable error by asserting ECSM_EEGR FRCNCI or ECSM_EEGR FRC1NCI and EC...

Page 315: ...e 2 bit data error in the internal SRAM is generated The assertion of this bit forces the internal SRAM controller to create one 2 bit data error as defined by the bit position specified in ERRBIT 0 6...

Page 316: ...d address 8 2 1 7 Flash ECC Master Number Register ECSM_FEMR The FEMR is an 8 bit register for capturing the XBAR bus master number of the last properly enabled ECC event in the Flash memory Depending...

Page 317: ...t is uninitialized Figure 8 5 Flash ECC Master Number Register ECSM_FEMR Table 8 7 ECSM_FEMR Field Descriptions Field Description 0 3 Reserved 4 7 FEMR 0 3 Flash ECC master number Contains the XBAR bu...

Page 318: ...multi bit non correctable ECC error is undefined 4 PROT0 Protection cache The reset value of this field is undefined 0 Non cacheable 1 Cacheable 5 PROT1 Protection buffer The reset value of this field...

Page 319: ...escriptions Field Description 0 31 FEDH 0 31 Flash ECC data Contains the data associated with the faulting access of the last properly enabled Flash ECC event The register contains the data value take...

Page 320: ...the state of the ECSM_ECR an ECC event in the RAM causes the address attributes and data associated with the access to be loaded into the ECSM_REAR ECSM_REMR ECSM_REAT and ECSM_REDRs and the appropri...

Page 321: ...XBAR bus master number of the faulting access of the last properly enabled RAM ECC event The reset value of this field is undefined Base 0x0067 Access Read 0 1 2 3 4 5 6 7 R WRITE SIZE PROT0 PROT1 PRO...

Page 322: ...ned 6 PROT2 Protection mode The reset value of this field is undefined 0 User mode 1 Supervisor mode 7 PROT3 Protection type The reset value of this field is undefined 0 I Fetch 1 Data Base 0x0068 Acc...

Page 323: ...ne The destination asserted an error the ESR XTE bit will be set The address where the error occurred using the data exception address register DEAR However details of the ECC error are not reported u...

Page 324: ...does not enable that its interrupt be recognized The INTC_PSR PRI value for the ECC error interrupt request is left at its reset value of 0 The 0 priority level is the lowest priority and is never rec...

Page 325: ...Error Correction Status Module ECSM MPC5565 Microcontroller Reference Manual Rev 1 0 8 16 Freescale Semiconductor...

Page 326: ...of performing complex data transfers with minimal intervention from a host processor 9 1 1 Overview The enhanced direct memory access eDMA controller hardware microarchitecture includes a DMA engine w...

Page 327: ...ead from source write to destination Programmable source destination addresses transfer size plus support for enhanced addressing modes 32 channel implementation performs complex data transfers with m...

Page 328: ...tion of major iteration count Error terminations are enabled per channel and logically summed together to form a single error interrupt Support for scatter gather DMA processing Any channel can be pro...

Page 329: ...le request register 8 Base 0x0019 EDMA_CERQR eDMA clear enable request register 8 Base 0x001A EDMA_SEEIR eDMA set enable error interrupt register 8 Base 0x001B EDMA_CEEIR eDMA clear enable error inter...

Page 330: ...r 8 Base 0x0114 EDMA_CPR20 eDMA channel 20 priority register 8 Base 0x0115 EDMA_CPR21 eDMA channel 21 priority register 8 Base 0x0116 EDMA_CPR22 eDMA channel 22 priority register 8 Base 0x0117 EDMA_CP...

Page 331: ...ol descriptor 14 256 Base 0x11E0 TCD15 eDMA transfer control descriptor 15 256 Base 0x1200 TCD16 eDMA transfer control descriptor 16 256 Base 0x1220 TCD17 eDMA transfer control descriptor 17 256 Base...

Page 332: ...channel service requests in the highest priority group are executed first where priority level 1 is the highest and priority level 0 is the lowest The group priorities are assigned in the GRPnPRI fiel...

Page 333: ...en the link is attempted if the TCD CITER E_LINK bit does not equal the TCD BITER E_LINK bit All configuration error conditions except scatter gather and minor loop link error are reported as the chan...

Page 334: ...13 14 15 R VLD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R GPE CPE ERRCHN SAE SOE DAE DOE NCE SGE SBE DBE W Reset 0 0 0 0 0...

Page 335: ...he last recorded error was a configuration error detected in the TCD DADDR field indicating TCD DADDR is inconsistent with TCD DSIZE 27 DOE Destination offset error 0 No destination offset configurati...

Page 336: ...0 The state of any given channel s error interrupt enable is directly affected by writes to these registers it is also affected by writes to the EDMA_SEEIR and EDMA_CEEIR The EDMA_SEEIR and EDMA_CEEI...

Page 337: ...13 14 15 R EEI31 EEI30 EEI29 EEI28 EEI27 EEI26 EEI25 EEI24 EEI23 EEI22 EEI21 EEI20 EEI19 EEI18 EEI17 EEI16 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R EE...

Page 338: ...MA_EEIRL to enable the error interrupt for a given channel The data value on a register write causes the corresponding bit in the EDMA_EEIRL to be set Setting bit 1 SEEIn provides a global set functio...

Page 339: ...ess Base 0x001A Access User W O 0 1 2 3 4 5 6 7 R 0 0 0 0 0 0 0 0 W SEEI 0 6 Reset 0 0 0 0 0 0 0 0 Figure 9 8 eDMA Set Enable Error Interrupt Register EDMA_SEEIR Table 9 8 EDMA_SEEIR Field Description...

Page 340: ...given bit in the EDMA_ERL to disable the error condition flag for a given channel The given value on a register write causes the corresponding bit in the EDMA_ERL to be cleared Setting bit 1 CERRn pr...

Page 341: ...eads of this register return all zeroes Table 9 11 EDMA_CER Field Descriptions Field Description 0 Reserved 1 7 CERR 0 6 Clear error indicator 0 31 Clear corresponding bit in EDMA_ERL 32 63 Reserved 6...

Page 342: ...the execution of the interrupt service routine associated with any given channel it is software s responsibility to clear the appropriate bit negating the interrupt request Typically a write to the ED...

Page 343: ...lso be polled and a non zero value indicates the presence of a channel error regardless of the state of the EDMA_EEIR The EDMA_ESR VLD bit is a logical OR of all bits in this register and it provides...

Page 344: ...tion 0 31 ERRn eDMA Error n 0 An error in channel n has not occurred 1 An error in channel n has occurred Address Base 0x0034 Access User R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R HRS3 1 HRS3 0 HRS2...

Page 345: ...le 9 2 for the EDMA_CR definition Channel preemption is enabled on a per channel basis by setting the ECP bit in the EDMA_CPRn register Channel preemption allows the executing channel s data transfers...

Page 346: ...y fields is equal to the corresponding channel number for each priority register that is EDMA_CPR31 GRPPRI 0b01 4 7 CHPRI 0 3 Channel n arbitration priority Channel priority when fixed priority arbitr...

Page 347: ...ntrol BWC 0x1000 32 x n 242 6 Link Channel Number MAJOR LINKCH 0x1000 32 x n 248 1 Channel Done DONE 0x1000 32 x n 249 1 Channel Active ACTIVE 0x1000 32 x n 250 1 Channel to channel Linking on Major L...

Page 348: ...21 22 23 24 25 26 27 28 29 30 31 0x0 SADDR 0x4 SMOD SSIZE DMOD DSIZE SOFF 0x8 NBYTES 0xC SLAST 0x10 DADDR 0x14 CITER E_ LINK CITER1 or CITER LINKCH 1 If channel linking on minor link completion is dis...

Page 349: ...bit x 4 110 Reserved 111 Reserved The attempted specification of a reserved encoding causes a configuration error 40 44 0x4 8 12 DMOD 0 4 Destination address modulo Refer to the SMOD 0 5 definition 45...

Page 350: ...or the channel It is decremented each time the minor loop is completed and updated in the transfer control descriptor memory After the major iteration count is exhausted the channel performs a number...

Page 351: ...hannel service request at the channel defined by BITER LINKCH 0 5 by setting that channel s TCD START bit Note When the TCD is first loaded by software this field must be set equal to the correspondin...

Page 352: ...other channel defined by MAJOR LINKCH 0 5 The link target channel initiates a channel service request via an internal mechanism that sets the TCD START bit of the specified channel NOTE To support the...

Page 353: ...the registers of the other address path channel x y After the inner minor loop completes execution the address path hardware writes the new values for the TCDn SADDR DADDR CITER back into the local m...

Page 354: ...e control functions for the eDMA engine For data transfers where the source and destination sizes are equal the eDMA engine performs a series of source read destination write operations until the numb...

Page 355: ...address to access the TCD local memory Next the TCD memory is accessed and the required descriptor read from the local memory and loaded into the eDMA engine address path channel x y registers The TC...

Page 356: ...ration count is exhausted then there are additional operations which are performed These include the final address adjustments and reloading of the BITER field into the CITER Additionally assertion of...

Page 357: ...environment the speed of the source and destination address spaces remains important but the microarchitecture of the eDMA also factors significantly into the resulting metric The peak transfer rates...

Page 358: ...in the eDMA module and qualified TCD START bit initiated requests start at this point with the registering of the slave write to TCD bit 255 Cycle 3 Channel arbitration begins Cycle 4 Channel arbitrat...

Page 359: ...its are checked and processed if enabled Cycle n 3 The appropriate fields in the first part of the TCDn are written back into the local memory Cycle n 4 The fields in the second part of the TCDn are w...

Page 360: ...s on the system bus from a cold start no channel is executing eDMA is idle are the following 11 cycles for a software TCD START bit request 12 cycles for a hardware eDMA peripheral request signal requ...

Page 361: ...ADDR and TCD CITER are written back to the main TCD memory and any minor loop channel linking is performed if enabled If the major loop is exhausted further post processing is executed for example int...

Page 362: ...number causing the error is recorded in the EDMA_ESR If the error source is not removed before the next activation of the problem channel the error is detected and recorded again DMA Request Minor Lo...

Page 363: ...pt request line contain undefined data because the channel is undefined A group priority error is global and any request in any group causes a group priority error If priority levels are not unique th...

Page 364: ...SPID SR TFFF DSPID Transmit FIFO Fill Flag DSPID_SR_RFDF 17 DSPID SR RFDF DSPID Receive FIFO Drain Flag eSCIA_COMBTX 18 ESCIA SR TDRE ESCIA SR TC ESCIA SR TXRDY eSCIA combined DMA request of the Trans...

Page 365: ...ed fixed arbitration Excessive request rates on high priority channels can prevent the servicing of lower priority channels in the same group 9 4 4 3 Round Robin Group Arbitration Round Robin Channel...

Page 366: ...The source memory has a byte wide memory port located at 0x1000 The destination memory has a word wide port located at 0x2000 The address offsets are programmed in increments to match the size of the...

Page 367: ...s with the exception of transferring 32 bytes via two hardware requests The only fields that change are the major loop iteration count and the final address offsets The eDMA is programmed for two iter...

Page 368: ...l 9 Second hardware eDMA peripheral request requests channel service 10 The channel is selected by arbitration for servicing 11 eDMA engine writes TCD DONE 0 TCD START 0 TCD ACTIVE 1 12 eDMA engine re...

Page 369: ...for minor loop completion when using software initiated service requests The first method is to read the TCD CITER field and test for a change Another method can be extracted from the following sequen...

Page 370: ...tion is selected for both group and channel arbitration modes A preempt able situation is one in which a preempt enabled channel is running and a higher priority request becomes active When the eDMA e...

Page 371: ...t The bits associated with the TCD CITER LINKCH field are concatenated onto the CITER value to increase the range of the CITER NOTE After configuration the TCD CITER E_LINK bit and the TCD BITER E_LIN...

Page 372: ...INK is set in the programmer s model but it is unclear whether the link completed before the channel retired Use the following coherency model when executing a dynamic channel link or dynamic scatter...

Page 373: ...ram added this footnote to the CITER and BITER fields If channel linking on minor link completion is disabled TCD bits 161 175 are used to form a 15 bit CITER field if channel to channel linking is en...

Page 374: ...pheral interrupt requests1 n1 Priority arbitrator n1 Highest priority interrupt requests n1 Request selector Lowest vector interrupt request n1 Vector encoder Interrupt vector 9 x 4 bits Interrupt ack...

Page 375: ...systems The INTC is optimized for a large number of interrupt requests It is targeted to work with a PowerPC book E processor and automotive powertrain applications where the ISRs nest to multiple lev...

Page 376: ...s the maximum number of usable interrupt vectors which equals 231 and includes 16 reserved IRQ vectors and eight software settable IRQ vectors Because the memory is mapped in four byte words the total...

Page 377: ...the work involved in servicing an interrupt request into a high priority portion and a low priority portion The high priority portion is initiated by a peripheral interrupt request but then the ISR c...

Page 378: ...equest and negates the interrupt request to the processor The interrupt request to the processor does not clear if a higher priority interrupt request arrives Even in this case INTVEC does not update...

Page 379: ...interrupt vector number Figure 10 6 Hardware Vector Mode Interrupt Exception Handler Address Calculation The processor negates INTC s interrupt request when automatically acknowledging the interrupt...

Page 380: ...OTCFG 0 1 _ P Boot configuration input I IRQ 2 3 _ A External interrupt request I BOOTCFG Down Down GPIO 211 212 G GPIO I O PLLCFG 0 _ P FMPLL mode selection I IRQ 4 _ A External interrupt request I P...

Page 381: ...Name Register Description Bits Base 0xFFF4_8000 INTC_MCR INTC module configuration register 32 Base 0x0004 Reserved Base 0x0008 INTC_CPR INTC current priority register 32 Base 0x000C Reserved Base 0x...

Page 382: ...read In either software or hardware vector mode the size of a write to the INTC end of interrupt register INTC_EOIR does not affect the operation of the write 10 3 1 1 INTC Module Configuration Regist...

Page 383: ...esses An mbar or msync instruction is also necessary after accessing the resource but before lowering the PRI field Refer to Section 10 5 5 2 Ensuring Coherency Table 10 4 INTC_MCR Field Descriptions...

Page 384: ...are vector mode Therefore for future compatibility the TLB entry covering the INTC_IACKR must be configured to be guarded In software vector mode the INTC_IACKR must be read before setting MSR EE No s...

Page 385: ...to CLRn has no effect If a 1 is written to a pair SETn and CLRn bits at the same time CLRn is asserted regardless of whether CLRn was asserted before the write Address Base 0x0010 INTC_IACKR Access R...

Page 386: ...e accessed with a single 16 bit or 32 bit access provided that the access does not cross a 32 bit boundary NOTE The PRIn field of an INTC_PSRn must not be modified while its corresponding peripheral o...

Page 387: ...ty select Selects the priority for corresponding interrupt request 1111 Priority 15 highest 1110 Priority 14 0001 Priority 1 0000 Priority 0 lowest Table 10 9 MPC5565 Interrupt Request Sources Hardwar...

Page 388: ...rupt 13 0x0190 25 EDMA_IRQRL INT14 eDMA channel interrupt 14 0x01A0 26 EDMA_IRQRL INT15 eDMA channel interrupt 15 0x01B0 27 EDMA_IRQRL INT16 eDMA channel interrupt 16 0x01C0 28 EDMA_IRQRL INT17 eDMA c...

Page 389: ...s 15 4 eMIOS 0x0330 51 EMIOS_GFR F0 eMIOS channel 0 flag 0x0340 52 EMIOS_GFR F1 eMIOS channel 1 flag 0x0350 53 EMIOS_GFR F2 eMIOS channel 2 flag 0x0360 54 EMIOS_GFR F3 eMIOS channel 3 flag 0x0370 55 E...

Page 390: ...0 80 ETPU_CISR_A CIS12 eTPU engine A channel 12 interrupt status 0x0510 81 ETPU_CISR_A CIS13 eTPU engine A channel 13 interrupt status 0x0520 82 ETPU_CISR_A CIS14 eTPU engine A channel 14 interrupt st...

Page 391: ...ADC command FIFO 1 non coherency flag 0x06B0 107 EQADC_FISR1 PF eQADC command FIFO 1 pause flag 0x06C0 108 EQADC_FISR1 EOQF eQADC command FIFO 1 command queue end of queue flag 0x06D0 109 EQADC_FISR1...

Page 392: ...0x0840 132 DSPI_BSR EOQF DSPI B transmit FIFO end of queue flag 0x0850 133 DSPI_BSR TFFF DSPI B transfer complete 0x0860 134 DSPI_BSR TCF DSPI B Rx FIFO drain request 0x0870 135 DSPI_BSR RFDF DSPI B...

Page 393: ...or Frame complete interrupts requests Receive register overflow 0x0930 0x0940 147 148 Reserved 0x0950 149 ESCIB_SR TDRE ESCIB_SR TC ESCIB_SR RDRF ESCIB_SR IDLE ESCIB_SR OR ESCIB_SR NF ESCIB_SR FE ESCI...

Page 394: ...BUF9 FlexCAN A buffer 9 interrupt 0x0A50 165 CANA_IFRL BUF10 FlexCAN A buffer 10 interrupt 0x0A60 166 CANA_IFRL BUF11 FlexCAN A buffer 11 interrupt 0x0A70 167 CANA_IFRL BUF12 FlexCAN A buffer 12 inte...

Page 395: ...C_IFRL BUF31 BUF16 FlexCAN C buffers 31 16 interrupts 0x0C10 193 CANC_IFRH BUF63 BUF32 FlexCAN C buffers 63 32 interrupts 0x0C20 0x0C90 194 201 Reserved eMIOS 0x0CA0 202 EMIOS_GFR F16 eMIOS channel 16...

Page 396: ...F3 FlexCAN B buffer 3 interrupt 0x11F0 287 CANB_IFRL BUF4 FlexCAN B buffer 4 interrupt 0x1200 288 CANB_IFRL BUF5 FlexCAN B buffer 5 interrupt 0x1210 289 CANB_IFRL BUF6 FlexCAN B buffer 6 interrupt 0x1...

Page 397: ...an interrupt request within the INTC just like a peripheral interrupt request An interrupt request is triggered by software writing a 1 to the SETn bit in INTC software set clear interrupt registers I...

Page 398: ...it is passed as asserted to the vector encoder submodule If multiple interrupt requests from the priority arbitrator submodule are asserted then only the one with the lowest vector is passed as assert...

Page 399: ...ng in software vector mode along with the handshaking near the end of the interrupt exception handler is shown in Figure 10 14 The INTC examines the peripheral and software settable interrupt requests...

Page 400: ...peripheral and software settable interrupt requests and when it finds an asserted one with a higher priority than PRI in INTC_CPR it asserts the interrupt request to the processor The INTVEC field in...

Page 401: ...ests are negated An initialization sequence for allowing the peripheral and software settable interrupt requests to cause an interrupt request to the processor is interrupt_request_initialization conf...

Page 402: ...LIFO after the restoration of most of the context and the disabling of processor recognition of interrupts eases the calculation of the maximum stack depth at the cost of postponing the servicing of t...

Page 403: ...ar ensure store to clear flag bit has completed lis r3 INTC_EOIR ha form adjusted upper half of INTC_EOIR address li r4 0x0 form 0 to write to INTC_EOIR wrteei 0 disable processor recognition of inter...

Page 404: ...ough to cause preemption the INTC selects the one with the lowest unique vector regardless of the order in time that they asserted However the ability to meet deadlines with this scheduling scheme is...

Page 405: ...that all higher priority interrupts are blocked For example while ISR3 cannot preempt ISR1 while it is accessing the shared resource all of the ISRs with a priority higher than 3 can preempt ISR1 10...

Page 406: ...this case group the ISRs with other ISRs that have similar deadlines For example a priority could be allocated for every time the request rate doubles ISRs with request rates around 1 ms would share a...

Page 407: ...ed that processor executing the software settable ISR has not completed the work before asking it to again execute that ISR it can check if the corresponding CLRn bit in INTC_SSCIRn is asserted before...

Page 408: ...es of the peripheral or software settable interrupt requests for these other flag bits must be selected properly Their PRIn values in INTC priority select registers INTC_PSR0 INTC_PSR231 must be selec...

Page 409: ...ower than the priorities of those peripheral or software settable interrupt requests 10 6 Document Revision History Table 10 11 Changes Between MPC5565RM Revisions 0 1 and 1 Changed the NOTE at the en...

Page 410: ...rocessor recognition of all interrupts reduces the priority inversion time when accessing a shared resource To Using the PCP instead of disabling processor recognition of all interrupts eliminates the...

Page 411: ...urable IRQs and 16 reserved IRQs Figure 10 3 Program Flow Software Vector Mode Added footnote 1 in text frame inside figure that reads N is the maximum number of usable interrupt vectors which equals...

Page 412: ...iagrams This section contains block diagrams that illustrate the FMPLL the clock architecture and the various FMPLL and clock configurations that are available The following diagrams are provided Figu...

Page 413: ...FM control 1 0 pumps Current controlled oscillator ICO XTAL 0 1 MFD PLLCFG 0 1 MDIS DSPI MCKO_EN MCKO_GT MCKO divider MCKO MDIS EBI MDIS eMIOS MDIS eTPU engines MDIS eSCI MDIS CAN interface CLK FlexC...

Page 414: ...0 pumps Current controlled oscillator ICO XTAL MFD PLLCFG 0 1 MDIS DSPI MCKO_EN MCKO_GT MCKO divider MCKO MDIS EBI MDIS eMIOS MDIS eTPU engines MDIS eSCI MDIS CAN interface CLK FlexCAN CLK_SRC Message...

Page 415: ...divider MCKO MDIS EBI MDIS eMIOS MDIS eTPU engines MDIS eSCI MDIS CAN interface CLK FlexCAN CLK_SRC Message buffer CLK ENGCLK divider CLKOUT divider ENGCLK CLKOUT NPC PLLREF PLLSEL MODE Core INTC eDMA...

Page 416: ...CKO divider MCKO MDIS EBI MDIS eMIOS MDIS eTPU engines MDIS eSCI MDIS CAN interface CLK FlexCAN CLK_SRC Message buffer CLK ENGCLK divider CLKOUT divider ENGCLK CLKOUT NPC PLLREF PLLSEL MODE Core INTC...

Page 417: ...MCKO MDIS EBI MDIS eMIOS MDIS eTPU engines MDIS eSCI MDIS CAN interface CLK FlexCAN CLK_SRC Message buffer CLK ENGCLK divider CLKOUT divider ENGCLK CLKOUT NPC PLLREF PLLSEL MODE Core INTC eDMA SIU BAM...

Page 418: ...LCFG 0 1 MDIS DSPI MCKO_EN MCKO_GT MCKO divider MCKO MDIS EBI MDIS eMIOS MDIS eTPU engines MDIS eSCI MDIS CAN Interface CLK FlexCAN CLK_SRC Message buffer CLK ENGCLK divider CLKOUT divider ENGCLK CLKO...

Page 419: ...96 assembly package Refer to Section 11 1 4 1 Crystal Reference Default Mode External reference mode Refer to Section 11 1 4 2 External Reference Mode PLL dual controller 1 1 mode for EXTAL_EXTCLK to...

Page 420: ...Chapter 4 Reset 11 1 4 1 Crystal Reference Default Mode In crystal reference mode the FMPLL receives an input clock frequency Fref_crystal from the crystal oscillator circuit EXTAL_EXTCLK and the pre...

Page 421: ...1 4 2 External Reference Mode This external reference mode functions the same as crystal reference mode except that EXTAL_EXTCLK is driven by an external clock generator rather than a crystal oscillat...

Page 422: ...o enter bypass mode the default FMPLL configuration must be overridden by following the procedure outlined in Section 11 1 4 FMPLL Modes of Operation A block diagram illustrating bypass mode is shown...

Page 423: ...for all MPC5500s execute an mbar or msync instruction between the write to change the FMPLL_SYNCR MFD and the read to check the lock status shown by FMPLL_SYNSR LOCK Buffered writes to the FMPLL as co...

Page 424: ...V bits In 1 1 dual controller mode the PREDIV bits are ignored and the input clock is fed directly to the analog loop 000 Divide by 1 001 Divide by 2 010 Divide by 3 011 Divide by 4 100 Divide by 5 10...

Page 425: ...e To avoid unintentional interrupt requests disable LOLIRQ before changing MFD and then reenable it after acquiring lock 9 Reserved 10 12 RFD 0 2 Reduced frequency divider The RFD bits control a divid...

Page 426: ...when it LOLIRQ is asserted and when LOLF is asserted If either LOLF or LOLIRQ is negated the interrupt request is negated When operating in crystal reference external reference or dual controller mode...

Page 427: ...9 Expected difference value Holds the expected value of the difference of the reference and the feedback counters Refer to Section 11 4 3 3 FM Calibration Routine to determine the value of these bits...

Page 428: ...g an unintentional interrupt clear LOLIRQ before changing MFD or PREDIV or before enabling FM after a previous interrupt and relock occurred 23 LOC Loss of clock status Indicates whether a loss of clo...

Page 429: ...ains cleared after reset In crystal reference external reference and dual controller mode LOCKS is set after reset 0 PLL has lost lock since last system reset a write to FMPLL_SYNCR to modify the MFD...

Page 430: ...can be selected as the clock source for the CAN interface in the FlexCAN blocks resulting in very low jitter performance Figure 11 1 shows a block diagram of the FMPLL and the system clock architectur...

Page 431: ...re enabled when the MCU comes out of reset 11 4 1 3 Clock Dividers Each of the CLKOUT MCKO and ENGCLK dividers provides a nominal 50 duty cycle clock to an output pin There is no guaranteed phase rela...

Page 432: ...g Clock ENGCLK The engineering clock ENGCLK divider can be programmed to divide the system clock by factors from 2 to 126 in increments of two The ENGDIV bit field in the SIU_ECCR determines the divid...

Page 433: ...tion A pair of counters monitor the reference and feedback clocks to determine when the system has acquired frequency lock After the FMPLL has locked the counters continue to monitor the reference and...

Page 434: ...de the FMPLL cannot lock Therefore a loss of lock condition cannot occur and LOLRE has no effect 11 4 2 5 2 FMPLL Loss of Lock Interrupt Request The FMPLL provides the ability to request an interrupt...

Page 435: ...a loss of clock condition is recognized reset is asserted if the FMPLL_SYNCR LOCRE bit is set The LOCF and LOC bits in FMPLL_SYNSR are cleared after reset therefore the SIU_RSR must be read to determ...

Page 436: ...requency without frequency modulation 1 Determine the value for the PREDIV MFD and RFD fields in the synthesizer control register FMPLL_SYNCR Remember to include the Fm if frequency modulation is enab...

Page 437: ...nal system frequency by changing FMPLL_SYNCR RFD The FMPLL does not need to re lock if only the RFD changes and the RFD must be set to greater than one to protect from overshoot 5 Reenable LOLIRQ NOTE...

Page 438: ...after the predivider Fmod Fref_crystal or Fref_ext PREDIV 1 x Q where Q 40 or 80 This gives modulation rates of 200 kHz and 100 kHz respectively NOTE If a 40 MHz input is used PLLCFG2 must equal 1 Af...

Page 439: ...not need to re lock when only changing the RFD 8 Re enable LOLIRQ NOTE This first register write causes the FMPLL to switch to an initial frequency which is less than the final one Keeping the change...

Page 440: ...is the expected value of the difference between the reference and feedback counters used in the calibration of the FM equation For example if 80 MHz is the desired final frequency and an 8 MHz crysta...

Page 441: ...back counter is disabled and the result is placed in the COUNT0 register The calibration system then enables modulation at programmed Fm The ICO is given time to settle Both counters are reset and res...

Page 442: ...re 11 11 shows a block diagram of the calibration circuitry and its associated registers Figure 11 12 shows a flow chart showing the steps taken by the calibration circuit Figure 11 11 FM Auto Calibra...

Page 443: ...counter Allow system 3 x 384 reference counts to settle CAL N 1 Enable FM N 7 Count M reference clock cycles Store value of feedback Counter in CAL 0 Enter calibration mode Set PCALPASS 1 Let DIFF CA...

Page 444: ...oes not reflect the current condition of the FMPLL If operating in bypass mode LOCK remains cleared after reset Refer to the for frequency as defined in the Data Sheet for the lock unlock range 0 PLL...

Page 445: ...Frequency Modulated Phase Locked Loop and System Clocks FMPLL MPC5565 Microcontroller Reference Manual Rev 1 0 11 34 Freescale Semiconductor...

Page 446: ...l bus interface EBI which handles the transfer of information between the internal buses and the memories or peripherals in the external address space and enables an external master to access internal...

Page 447: ...ct signals CS 0 3 _ADDR 8 11 _GPIO 0 3 ADDR 8 11 is also muxed with GPIO 4 7 providing four chip selects and 24 bit address bits ADDR 8 11 _GPIO 4 7 no balls available Use CS 0 3 _ADDR 8 11 _GPIO 0 3...

Page 448: ...al master controller Bus monitor Registers Slave interface CLKOUT driver CLKOUT crossbar switch XBAR Master interface crossbar switch XBAR Peripheral bridge CS 0 3 1 TS OE BDIP TA TEA 1 WE BE 0 3 1 PB...

Page 449: ...DDR 12 31 is the default pin set then CS 0 3 _ADDR 8 11 _GPIO 0 3 must be configured by PCR to ADDR 8 11 to attain the 24 bit size 20 bits 2 2 20 bits is the default EBI size for the 324 package ADDR...

Page 450: ...dule Configuration Register EBI_MCR for details Configurable bus speed modes and debug mode are modes that the MCU can enter in parallel to the EBI being configured in one of its module specific modes...

Page 451: ...ther than the internal system clock This mode is selected by writing the external clock control register in the system integration module SIU_ECCR The configurable bus speed modes supports both 1 2 or...

Page 452: ...kage limitations 4963 assembly 3 All EBI and calibration signals designed for this device are available on the VertiCal assembly ADDR 8 11 2 3 I O Address bus Up 324 2 4 496 ADDR 12 31 I O Address bus...

Page 453: ...s a write transaction to an external device The EBI also drives DATA 0 31 when an external master owns the external bus and initiates a read transaction to an internal module DATA 0 31 is driven by an...

Page 454: ...ion bus access the CS signals are held negated 12 2 1 6 Output Enable OE OE is used to indicate when an external memory is permitted to drive back read data External memories must have their data outp...

Page 455: ...al master depending on who owns the external bus TS is only asserted for the first clock cycle of the transaction and is negated in the successive clock cycles until the end of the transaction During...

Page 456: ...t driven by the EBI during a calibration bus access During a calibration bus access the non calibration bus signals other than DATA are held in a negated state with the exception of RD_WR and ADDR whi...

Page 457: ...t a 32 bit EBI data bus DATA 0 31 and four write byte enable signals WE BE 0 3 on the VertiCal assembly The 324 package provides a 16 bit EBI data bus DATA 0 16 and two write byte enable signals WE BE...

Page 458: ...register bank 0 32 Base 0x0014 EBI_OR0 EBI option register bank 0 32 Base 0x0018 EBI_BR1 EBI base register bank 1 32 Base 0x001C EBI_OR1 EBI option register bank 1 32 Base 0x0020 EBI_BR2 EBI base reg...

Page 459: ...m the clock used by the rest of the EBI In module disable mode the clock used by the non register portion of the EBI is disabled to reduce power consumption The clock signal dedicated to the registers...

Page 460: ...gating is disabled 1 Automatic CLKOUT gating is enabled 17 EXTM External master mode The EBI module must be enabled MDIS 0 to configure the external master mode When the EBI module is disabled MDIS 1...

Page 461: ...error status register Base 0x0008 Access R W1c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29...

Page 462: ...1 1 1 1 0 0 0 0 0 0 0 Figure 12 4 EBI Bus Monitor Control Register EBI_BMCR Table 12 9 EBI_BMCR Field Descriptions Field Description 0 15 Reserved 16 23 BMT 0 7 Bus monitor timing Defines the timeout...

Page 463: ...0 0 0 0 1 0 Figure 12 5 EBI Base Registers 0 3 EBI_BRn and EBI Calibration Base Registers 0 3 EBI_CAL_BRn Table 12 10 EBI_BRn and EBI_CAL_BRn Field Descriptions Field Description 0 16 BA 0 16 Base ad...

Page 464: ...configuration 1 Only assert BDIP BSCY 1 external bus cycles before expecting subsequent burst data beats 28 29 Reserved 30 BI Burst inhibit Determines whether or not burst read accesses are allowed f...

Page 465: ...BI_CAL_ORn Field Descriptions Field Description 0 16 AM 0 16 Address mask Allows masking of any corresponding bits in the associated base register Masking the address independently allows external dev...

Page 466: ...ernal Addresses The EBI allows an external master to access internal address space when the EBI is configured for external master mode in the EBI_MCR External master operations are described in detail...

Page 467: ...cture A match on a valid calibration chip select register overrides a match on any non calibration chip select register with CAL_CS 0 having the highest priority Thus the full priority of the chip sel...

Page 468: ...ne externally are broken up into separate 32 bit or 16 bit external transactions according to the port size Refer to Section 12 4 2 6 Small Accesses Small Port Size and Short Burst Length for more det...

Page 469: ...e pins as BE 0 3 while clearing them to 0 configures them as WE 0 3 WE 0 3 signals are asserted only during write accesses while BE 0 3 signals are asserted for both read and write accesses The timing...

Page 470: ...to Section 12 1 4 Modes of Operation for a description of the power saving modes 12 4 1 17 Optional Automatic CLKOUT Gating The EBI has the ability to hold the external CLKOUT pin high when the EBI s...

Page 471: ...e external bus the bus cycles provided for data transfer operations bus arbitration and error conditions 12 4 2 1 External Clocking The CLKOUT signal sets the frequency of operation for the bus interf...

Page 472: ...ntentions when switching between drivers The master must start driving write data one cycle after the address transfer cycle The master can stop driving the data bus as soon as it samples the TA line...

Page 473: ...Beat Read Cycle Figure 12 10 Single Beat 32 bit Read Cycle CS Access Zero Wait States Yes No Receives address Asserts transfer start TS drives address and attributes Master EBI Drives data Asserts tra...

Page 474: ...Figure 12 12 Single Beat 32 bit Read Cycle Non CS Access Zero Wait States Wait state DATA is valid CLKOUT ADDR 8 31 TS DATA 0 31 TA RD_WR BDIP OE CS n DATA is valid The EBI drives address and control...

Page 475: ...le beat write cycle are illustrated in the following flow and timing diagrams Figure 12 13 Basic Flow Diagram of a Single Beat Write Cycle Yes No Receives address Asserts transfer start TS drives addr...

Page 476: ...r 12 31 Figure 12 14 Single Beat 32 bit Write Cycle CS Access Zero Wait States Figure 12 15 Single Beat 32 bit Write Cycle CS Access One Wait State DATA is valid CLKOUT ADDR 8 31 TS DATA 0 31 TA RD_WR...

Page 477: ...to Figure 12 20 and Figure 12 21 Besides this dead cycle in most cases back to back accesses on the external bus do not cause any change in the timing from that shown in the previous diagrams and the...

Page 478: ...ctor 12 33 Figure 12 17 Back to Back 32 bit Reads to the Same CS Bank Figure 12 18 Back to Back 32 bit Reads to Different CS Banks DATA is valid DATA is valid CLKOUT ADDR 8 31 TS DATA 0 31 TA RD_WR BD...

Page 479: ...face EBI MPC5565 Microcontroller Reference Manual Rev 1 0 12 34 Freescale Semiconductor Figure 12 19 Write After Read to the Same CS Bank ADDR 8 31 TS DATA 0 31 TA RD_WR DATA is valid BDIP WE CS n DAT...

Page 480: ...EBI MPC5565 Microcontroller Reference Manual Rev 1 0 Freescale Semiconductor 12 35 Figure 12 20 Back to Back 32 bit Writes to the Same CS Bank CLKOUT ADDR 8 31 TS DATA 0 31 TA RD_WR BDIP WE CS n DATA...

Page 481: ...ccesses to external devices that use the chip selects1 Accesses from an external master or to devices operating without a chip select are always single beat If an internal request to the EBI indicates...

Page 482: ...by the EBI so the EBI does not allow other unrelated master accesses or bus arbitration to intervene between the transfers For more details and a timing diagram refer to Section 12 4 2 6 3 Small Acce...

Page 483: ...12 22 Basic Flow Diagram of a Burst Read Cycle No Yes Receives address Asserts transfer start TS Drives address and attributes Master Next to last data beat Slave Drives data Asserts transfer acknowle...

Page 484: ...2 23 Burst 32 bit Read Cycle Zero Wait States Figure 12 24 Burst 32 bit Read Cycle One Initial Wait State CLKOUT ADDR 8 31 BDIP DATA 0 31 TA RD_WR TS OE CS n Expects more data ADDR 29 31 000 DATA is v...

Page 485: ...te EBI base register results in BDIP being asserted SCY 1 cycles after the address transfer phase and being held asserted throughout the cycle regardless of the wait states between beats BSCY Figure 1...

Page 486: ...bit EBI_BRn PS are set such that one of two situations occur Burst accesses are inhibited and the number of bytes requested by the master is greater than the port size 16 or 32 bit can accommodate in...

Page 487: ...2 Small Access Example 2 32 byte Write with External TA The following sections show a few examples of small accesses The timing for the remaining cases in Table 12 15 can be extrapolated from these a...

Page 488: ...ss Example 1 32 bit Write to 16 bit Port Figure 12 27 shows an example of a 32 bit write to a 16 bit port requiring two 16 bit external transactions Figure 12 27 Single Beat 32 bit Write Cycle 16 bit...

Page 489: ...the end of a 64 bit boundary In this case an extra cycle is required between TA and the next TS to get the next 64 bits of write data internally and RD_WR negates during this extra cycle Figure 12 28...

Page 490: ...ing 0x10 to the lower 5 bits of the first address no carry and then masking out the lower 4 bits to fix them at zero Figure 12 29 32 Byte Read with Back to Back 16 Byte Bursts to 32 bit Port Zero Wait...

Page 491: ...gned external access In the erroneous case that an externally initiated misaligned access does occur the EBI errors the access by asserting TEA externally and does not initiate the access on the inter...

Page 492: ...al Operand Representation Figure 12 31 shows the device connections on the DATA 0 31 bus Figure 12 31 Interface to Different Port Size Devices OP0 OP1 OP2 0 31 32 bit 16 bit Byte OP0 OP1 OP2 OP3 OP0 O...

Page 493: ...7 D 8 15 Byte 01 0 0 OP0 OP0 01 0 1 OP1 OP1 01 1 0 OP2 OP2 01 1 1 OP3 OP3 16 bit 10 0 0 OP0 OP1 OP0 OP1 10 1 0 OP2 OP3 OP2 OP3 32 bit 00 0 0 OP0 OP1 OP2 OP3 OP0 OP23 3 This case consists of two 16 bi...

Page 494: ...rnal pullup to drive TA For EBI mastered chip select accesses the EBI drives TA the entire cycle asserting according to internal wait state counters to terminate the cycle During idle periods on the e...

Page 495: ...ly before it detects the latched TEA assertion This means that non burst chip select accesses with no wait states SCY 0 cannot be reliably terminated by external TEA If external error termination is r...

Page 496: ...drives address and control signals an extra cycle because it uses a latched version of TA This is the earliest that the EBI can start another transfer in the case of continuing a set of small accesse...

Page 497: ...Connected to External Master and SDR Memory When the external master requires external bus accesses it takes ownership on the external bus and the direction of most of the bus signals is inverted rel...

Page 498: ...xternal master access to determine if EBI operation is required Because only 24 address bits are available on the external bus special decoding logic is required to allow an external master to access...

Page 499: ...d with either TA or TEA If the access was successfully completed the MCU asserts TA and the external master can proceed with another external master access or relinquish the bus If an address or data...

Page 500: ...igure 12 35 Basic Flow Diagram of an External Master Write Cycle EARB 1 External Master EBI Slave Receives address No Yes Address in internal memory map Other shared device Drives data Asserts transfe...

Page 501: ...ernal module is being accessed and how much internal bus traffic is going on at the time of the access Figure 12 36 External Master Read from MCU Figure 12 37 External Master Write to MCU CLKOUT RD_WR...

Page 502: ...ed in earlier sections for single master mode The following flow and timing diagrams show the basic single beat read case The remaining cases writes bursts etc can be observed in Section 12 4 2 4 Sing...

Page 503: ...h the EBI master and EBI slave as the external master is expected to be another MCU with this EBI For this case a special two beat burst protocol is used for reads and writes so that the EBI slave can...

Page 504: ...xternal Master 32 bit Read from MCU with DBM 1 Figure 12 41 External Master 32 bit Write to MCU with DBM 1 CLKOUT RD_WR BDIP ADDR 8 31 DATA 0 15 TS Input Minimum 2 wait states DATA is valid TA Output...

Page 505: ...switch from one bus to the other as determined by the type of chip select each address matches The timing diagrams and protocol for the calibration bus are identical to those for the primary bus exce...

Page 506: ...the following method Copy the code that is doing the register writes plus a return branch to internal SRAM Branch to internal SRAM to run this code ending with a branch back to external flash 12 5 2...

Page 507: ...to any chip select memory synchronous or asynchronous As an example say we have a memory with 50 ns access time and we are running the external bus at 66 MHz CLKOUT period 15 2 ns When the input data...

Page 508: ...gure 12 45 Read Operation to Asynchronous Memory Three Initial Wait States Flash memories typically use one WE signal as shown MCU Asynchronous Memory Note On a 32 bit bus RAM memories use all four WE...

Page 509: ...scale Semiconductor Figure 12 46 shows a timing diagram of a write operation to a 16 bit asynchronous memory using three wait states Figure 12 46 Write Operation to Asynchronous Memory Three Initial W...

Page 510: ...ual MCU systems for packages with reduced pin counts More than one section can apply if the pins are not present on one or both MCUs 12 5 5 1 Connecting 16 bit MCU to 32 bit MCU Master Master or Maste...

Page 511: ...ed on the slave MCU by setting SIZEN 1 in slave s EBI_MCR Anytime the master MCU needs to read or write the slave MCU with a different transfer size than the current value of the slave s SIZE field th...

Page 512: ...he BL field of the base register has inverted logic from the MPC56x devices 0 eight beat burst on the MPC5xxx 1 eight beat burst on the MPC56x Removed reservation support on external bus Removed addre...

Page 513: ...ch as the cases of back to back writes or read after write to the same chip select See Figure 12 20 and Figure 12 21 In Table 12 4 2 3 changed From To facilitate asynchronous write support the EBI kee...

Page 514: ...gnals designed for this device are available on the VertiCal assembly 5 ADDR 8 11 signals are muxed as alternate signals with the chip select CS 0 3 and GPIO 0 3 signals ADDR 8 11 are also available a...

Page 515: ...External Bus Interface EBI MPC5565 Microcontroller Reference Manual Rev 1 0 12 70 Freescale Semiconductor...

Page 516: ...llowing for field reprogramming without requiring external programming voltage sources The module is a solid state silicon memory device consisting of blocks of single transistor storage elements The...

Page 517: ...yed non volatile storage elements sense amplifiers row selects column selects charge pumps ECC logic and redundancy logic The arrayed storage elements in the flash core are subdivided into physically...

Page 518: ...tion of other memory types The flash memory array has the following features Software programmable block program erase restriction control for low mid and high address spaces Erase of selected blocks...

Page 519: ...l flash has a feature that allows the internal flash timing to be modified to emulate an external memory hence the name external emulation mode The upper five address lines are used to provide additio...

Page 520: ...00 Array base address 0x0000_0000 Control registers base address 0xC3F8_8000 Table 13 2 Module Flash Array Memory Map Byte Address Type and Amount of Space Used Access Shadow base 0x0000_0000 Shadow b...

Page 521: ...x0001_C000 L3 16 KB Array base 0x0002_0000 L4 64 KB 2 Array base 0x0003_0000 L5 64 KB Array base 0x0004_0000 Mid address space M0 128 KB 3 Array base 0x0006_0000 M1 128 KB Array base 0x0008_0000 High...

Page 522: ...t support RWW Refer to Section 13 4 2 5 Flash Shadow Block Table 13 4 Module Register Memory Map Byte Address Register Name Register Description Bits Register base 0x0000 FLASH_MCR Module configuratio...

Page 523: ...0 0 0 SIZE 0 LAS 0 0 0 MAS W Reset 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 16 17 18 19 20 21 22 238 24 25 26 27 28 29 30 31 R EER RWE 1 1 PEAS DONE PEG 0 0 STOP 0 PGM PSUS ERS ESUS EHV W w1c w1c Reset 0 0 1 1...

Page 524: ...program erase and main address space disabled 21 DONE State machine status Indicates if the flash module is performing a high voltage operation DONE is set to a 1 on termination of the flash module r...

Page 525: ...rogram suspend and clear DONE while EHV is low PSUS is cleared on reset 0 Program sequence is not suspended 1 Program sequence is suspended 29 ERS Erase Used to set up flash for an erase operation A 0...

Page 526: ...EHV with DONE high PSUS and ESUS low terminates the current program erase high voltage operation When an operation is aborted2 there is a 1 to 0 transition of EHV with DONE low and the suspend bit fo...

Page 527: ...locks from being modified These bits along with bits in the secondary LMLOCK field FLASH_SLMLR determine if the block is locked from program or erase An OR of FLASH_LMLR and FLASH_SLMLR determine the...

Page 528: ...ess LME is high 0 Shadow row is available to receive program and erase pulses 1 Shadow row is locked for program and erase 12 13 Reserved 14 15 MLOCK 1 0 Mid address block lock A value of 1 in a bit o...

Page 529: ...ed by flash values in the shadow row An erased array causes the reset value to be 1 Figure 13 7 High Address Space Block Locking Register FLASH_HLR Table 13 8 FLASH_HLR Field Descriptions Field Descri...

Page 530: ...ow and mid address locks are disabled and cannot be modified 1 Secondary low and mid address locks are enabled to be written 1 10 Reserved 11 SSLOCK Secondary shadow lock An alternative method to use...

Page 531: ...write is completed or if a high voltage operation is suspended In the event that blocks are not present due to configuration or total memory size the corresponding SELECT bits default to unselected an...

Page 532: ...ptions Field Description 0 19 Reserved 20 31 HBSEL 11 0 High address space block select Has the same characteristics as MSEL For more information refer to Section 13 3 2 5 Low Mid Address Space Block...

Page 533: ...d as 0 Address Base 0xC3F8_8000 0x001C Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 M3 PFE M2 PFE M1 PFE M0 PFE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21...

Page 534: ...state control Used to control the flash array access time for array reads This field must be set to a value corresponding to the operating frequency of the system clock The required settings are docu...

Page 535: ...buffer hit or miss 111 Reserved 31 BFEN FBIU line read buffers enable Enables or disables line read buffer hits It is also used to invalidate the buffers These bits are cleared by hardware reset 0 The...

Page 536: ...read buffer fills Prefetch triggering can be restricted to instruction accesses only data accesses only or can be unrestricted Prefetch triggering can also be controlled on a per master basis Address...

Page 537: ...n of a protection violation results in an error response from the Flash BIU to the system bus 13 4 1 3 Flash Read Cycles Buffer Miss Read data is normally stored in the least recently updated line rea...

Page 538: ...valid data which has been prefetched to satisfy a potential future access Busy the buffer is currently being used to satisfy a burst read Busy fill the buffer has been allocated to receive data from t...

Page 539: ...for primary wait states When these inputs are non zero additional cycles are added to system bus transfers Normal system bus termination is extended In addition no line read buffer prefetches are init...

Page 540: ...13 3 2 4 Secondary Low Mid Address Space Block Locking Register FLASH_SLMLR for more information 13 4 2 2 Read While Write RWW The flash core is divided into partitions Partitions are always comprise...

Page 541: ...ammed write each additional address in the page with data to be programmed This is referred to as a program data write All unwritten data words default to 0xFFFF FFFF 4 Write a logic 1 to the FLASH_MC...

Page 542: ...module to step 8 of the program sequence An aborted program results in FLASH_MCR PEG being set low indicating a failed operation The data space being operated on before the abort contains indeterminat...

Page 543: ...0 User mode read state PEG 0 Read MCR DONE 1 DONE 0 Write MCR PSUS 0 EHV 1 Abort WRITE EHV 0 Step 5 Step 6 PEG Success PEG 1 Write MCR Failure PEG 0 Step 7 EHV 0 PGM More words Step 8 No Yes Write MCR...

Page 544: ...nded until FLASH_MCR DONE 1 At this time flash core reads can be attempted After it is suspended the flash core can only be read Reads to the blocks being programmed erased return indeterminate data T...

Page 545: ...e interlock writes are ignored The user can terminate the erase sequence by clearing FLASH_MCR ERS before setting FLASH_MCR EHV An erase operation can be aborted by clearing FLASH_MCR EHV assuming FLA...

Page 546: ...be read or a program sequence can be initiated erase suspended program Before initiating a program sequence the user must first clear FLASH_MCR EHV If a program sequence is initiated the value of the...

Page 547: ...e suspend ERS 0 User mode read state PEG 0 Read MCR DONE 1 DONE 0 Write MCR ESUS 0 EHV 1 Abort WRITE EHV 0 Step 5 Step 6 PEG Success PEG 1 Write MCR Failure PEG 0 Step 7 EHV 0 Erase more blocks Step 8...

Page 548: ...for user defined functions or other configuration words The shadow block can be locked unlocked against program or erase by using the FLASH_LMLR or FLASH_SLMLR discussed in Section 13 3 2 Register De...

Page 549: ...cess is disabled Flash access is any read write or execute access Table 13 16 Flash Access Disable Logic BOOTCFG1 0 1 1 BOOTCFG 0 1 bits are located in the SIU_RSR Censorship Control 0x00FF_FDE0 Upper...

Page 550: ...value to internal flash 13 4 3 Flash Memory Array Stop Mode Stop mode is entered by setting the FLASH_MCR STOP bit The FLASH_MCR STOP bit cannot be written when FLASH_MCR PGM 1 or FLASH_MCR ERS 1 In...

Page 551: ...ize register and status bits to their default reset values If the flash is executing a program or erase operation and a reset is issued the operation is aborted and the flash disables the high voltage...

Page 552: ...the FBIU and are forwarded to the system bus on the following cycle To and a 256 bit read data interface from the flash memory array If enabled the Flash BIU contains a two entry prefetch buffer each...

Page 553: ...Flash Memory MPC5565 Microcontroller Reference Manual Rev 1 0 13 38 Freescale Semiconductor...

Page 554: ...source for standby operation Byte halfword word and doubleword addressable Single bit correction and double bit error detection 14 2 SRAM Operating Modes Table 14 1 lists and describes the SRAM opera...

Page 555: ...rrects all 1 bit errors Detects and flags all 2 bit errors as non correctable errors Detects 72 bit reads 64 bit data bus plus the 8 bit ECC that return all zeros or all ones asserts an error indicato...

Page 556: ...operation Lists the type of SRAM operation executing currently Previous operation Lists the valid types of SRAM operations that can precede the current SRAM operation valid operation during the prece...

Page 557: ...write to each SRAM location in the application initialization code to initialize the SRAM array All writes must specify an even number of registers performed on 64 bit word aligned boundaries If the w...

Page 558: ...the use of the stmw instruction to initialize the SRAM ECC bits init_RAM lis r11 0x4000 base address of the SRAM 64 bit word aligned ori r11 r11 0 not needed for this address but could be for others...

Page 559: ...SRAM MPC5565 Microcontroller Reference Manual Rev 1 0 14 6 Freescale Semiconductor...

Page 560: ...ccupies the last 16 KB of the MCU memory space The BAM program supports several booting modes Internal flash External memory without bus arbitration Serial boot using an eSCI interface FlexCAN interfa...

Page 561: ...ponds to all read requests within its address space The BAM program is executed following the negation of reset 15 1 3 2 Debug Mode The BAM program is not executed when the MCU comes out of reset in O...

Page 562: ...0xFFFF_F000 A copy of the BAM code resides in the three preceding 4 KB segment as shown in Table 15 1 The BAM program executes from the reset vector at address 0xFFFF_FFFC Table 15 1 shows the addres...

Page 563: ...the reset status register SIU_RSR Censorship control field located at 0x00FF_FDE0 in the shadow row of internal flash Serial boot control field located at 0x00FF_FDE2 in the shadow row of internal fl...

Page 564: ...trol 0x00FF_FDE2 Boot Mode Name Internal Flash State Nexus State Serial Password 00 0x55AA1 1 NOT as in 0x55AA which means all values except 0x55AA Do not use 0x0000 or 0xFFFF for the value of the cen...

Page 565: ...d avoid a bus error The BAM program reads up to six addresses in internal flash to find a valid 16 bit reset configuration halfword RCHW If a valid RCHW is read the BAM program sets the e200z6 watchdo...

Page 566: ...boot vector address BOOT_BLOCK_ADDRESS 0x0000_0004 If the watchdog timer is enabled the watchdog timeout is set to 2 5 217 system clock periods 15 3 2 2 External Boot Modes Use external boot mode to...

Page 567: ...0 Bus Operation in External Master Mode Section 12 5 5 Dual MCU Operation with Reduced Pinout MCUs to implemen t a system with master and slave peripherals for a device with no arbitration pins 15 3 2...

Page 568: ...run in VLE mode When the VLE flag is set the BAM programs the external bus interface EBI RAM and the flash memory map unit MMU TLB entries 1 2 and 3 with the VLE attribute Clear the VLE bit to 0 for d...

Page 569: ...or information on FlexCAN bit rate generation Coming out of reset the default system clock is 1 5 times the crystal frequency The baud rate with PLL enabled is equal to the crystal frequency divided b...

Page 570: ...s with the sent data and restart the process if an error is detected Upon receiving a valid FlexCAN message with an ID equal to 0x011 that contains 8 data bytes or a valid eSCI message the BAM uses a...

Page 571: ...ial download password FlexCAN messages with other IDs or fewer bytes of data are ignored When a valid message is received the BAM transmits a FlexCAN message with ID 0x001 that contains the data recei...

Page 572: ...before switching to execute the code just loaded The start address is expected on a 32 bit word boundary therefore the least significant 2 bits of the address are ignored FlexCAN messages with other...

Page 573: ...alue that does not cause resets during normal operation 15 3 2 3 4 eSCI Serial Boot Mode Download Process The eSCI serial boot mode download process contains the following steps 1 Download the 64 bit...

Page 574: ...the password fails a validity test the MCU stops responding to all stimulus To repeat the boot operation assert the RESET signal or wait for the watchdog timer to reset the MCU If the password is vali...

Page 575: ...ed in step 2 and executes the code NOTE The code that downloads and executes must periodically refresh the e200z6 watchdog timer or change the timeout period to a value that does not cause resets duri...

Page 576: ...start address VLE flag and the number of data bytes to download Rewrote beginning of step 2 from the second bulleted list to read 2 Download the start address VLE bit and the download size The host c...

Page 577: ...Boot Assist Module BAM MPC5565 Microcontroller Reference Manual Rev 1 0 15 18 Freescale Semiconductor...

Page 578: ...Manual Rev 1 0 Freescale Semiconductor 16 1 Chapter 16 Enhanced Modular Input Output Subsystem eMIOS 16 1 Introduction This chapter describes the enhanced modular input output subsystem eMIOS which ca...

Page 579: ...ck Enhanced Modular Unified STAC client submodule BIU Slave interface Clock prescaler Output disable control bus Note 1 Connection between UC n 1 and UCn necessary to implement QDEC mode Input Output...

Page 580: ...l counter Internal prescaler Dedicated output pin for buffer direction control Selectable time base Can generate its own time base Four 24 bit wide counter buses Counter bus A can be driven by unified...

Page 581: ...modulation buffered These modes are described in Section 16 4 4 4 Unified Channels Operating Modes Table 16 1 eMIOS Operating Modes Mode Description User User mode is the normal operating mode When E...

Page 582: ...eMIOS Output Disable Input Signals 16 2 1 External Signals When configured as an input EMIOSn is synchronized and filtered by the programmable input filter PIF The output of the PIF is then used by t...

Page 583: ...annel has selected output disable capability by the setting of its EMIOS_CCRn ODIS bit and by specifying the output disable input in its EMIOS_CCRn ODISSL field eTPU Output Disable Input Signal3 3 ETP...

Page 584: ...ters 256 Base 0x0200 UC15 Unified channel 15 registers 256 Base 0x0220 UC16 Unified channel 16 registers 256 Base 0x0240 UC17 Unified channel 17 registers 256 Base 0x0260 UC18 Unified channel 18 regis...

Page 585: ...used to stop the clock of the module except the access to registers EMIOS_MCR and EMIOS_OUDR 0 Clock is running 1 Enter low power mode 2 FRZ Freeze Enables the eMIOS to freeze the registers in the uni...

Page 586: ...AC Client Submodule and the shared time and angle clock STAC bus interface section and the STAC bus configuration register ETPU_REDCR section of the eTPU chapter for more information about the STAC 5...

Page 587: ...F2 F1 F0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 16 3 eMIOS Global Flag Register EMIOS_GFR Address Base 0x0008 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 OU23 OU22 OU21...

Page 588: ...red by reset Table 16 8 summarizes the EMIOS_CBDRn writing and reading accesses for all operating modes Refer to Section 16 4 4 4 Unified Channels Operating Modes for more information NOTE The EMIOS_C...

Page 589: ...ster Access Write Read Write Read Alternate Read GPIO A1 A2 A1 B1 B2 B1 SAIC1 A2 B2 B2 SAOC1 1 In these modes the register EMIOS_CBDRn is not used but B2 can be accessed A2 A1 B2 B2 IPWM A2 B1 IPM A2...

Page 590: ...mong these controls are the setting of a channel prescaler channel mode selection input trigger sensitivity and filtering interrupt and DMA request enabling and output mode control Address UCn Base 0x...

Page 591: ...signal is asserted the output pin goes to the complement of EDPOL for OPWFM OPWFMB and OPWMB modes but the unified channel continues to operate normally that is it continues to produce FLAG and match...

Page 592: ...DMA 8 Reserved Table 16 9 EMIOS_CCRn Field Description continued Field Description eMIOS Channel DMA 0 DMA 1 0 Interrupt DMA request 1 Interrupt DMA request 2 Interrupt DMA request 3 Interrupt DMA re...

Page 593: ...cleared by reset and is always read as zero This bit is valid for every output operating mode which uses comparator A otherwise it has no effect 0 Has no effect 1 Force a match at comparator A For inp...

Page 594: ...OL bit When not shown in the mode of operation description this bit has no effect 0 Single edge triggering defined by the EDPOL bit 1 Both edges triggering For GPIO input mode the EDSEL bit selects if...

Page 595: ...he count direction according to the phase difference 0 Internal counter decrements if phase_A is ahead phase_B signal 1 Internal counter increments if phase_A is ahead phase_B signal NOTE To operate p...

Page 596: ...t pulse width and frequency modulation FLAG set at match of internal counter and comparator B immediate update 0011001 Output pulse width and frequency modulation FLAG set at match of internal counter...

Page 597: ...ncy modulation buffered FLAG set at match of internal counter and comparator B 1011001 Reserved 1011010 Output pulse width and frequency modulation buffered FLAG set at match of internal counter and c...

Page 598: ...el Status Register EMIOS_CSRn Table 16 11 EMIOS_CSRn Field Descriptions Field Description 0 OVR Overrun Indicates a FLAG was generated when the FLAG bit was set to 1 To clear the OVR bit write 1 to cl...

Page 599: ...be shared by the channels through four counter buses and each unified channel can generate its own time base Optionally the counter A bus can be driven by an external time base from the eTPU imported...

Page 600: ...ase imported from the STAC bus to the eMIOS unified channels The eTPU module s time bases and angle count can be exported and or imported through the STAC client submodule interface Time bases and or...

Page 601: ...re is no freeze function in this submodule 16 4 3 Global Clock Prescaler Submodule GCP The global trace prescaler divides the system clock to generate a clock for the unified channels The system clock...

Page 602: ...events to occur before software intervention is needed Two comparators equal only A and B that compare the selected counter bus with the value in the data registers Internal counter for use as a loca...

Page 603: ...DATE Output disable control bus ODISSL 0 1 EMIOSn EMIOSn Internal bus Unified channel Counter bus select Internal counter Register A1 Register A2 Register B1 Register B2 Notes 1 Counter bus A can be d...

Page 604: ...rs in this signal the 5 bit counter starts counting up As long as the new state is stable on the pin the counter continues incrementing If a counter overflows occurs the new pin value is validated In...

Page 605: ...y input events that occurs while the channel is frozen are ignored When exiting debug mode or freeze enable bit is cleared FRZ in the EMIOS_MCR or FREN in the EMIOS_CCRn the channel actions resume 16...

Page 606: ...l is used as a single output port pin and the value of the EDPOL bit is permanently transferred to the output flip flop NOTE The GPIO modes provided in the eMIOS are particularly useful as interim mod...

Page 607: ...the value in EDPOL is transferred to it At the same time the FLAG bit is set to indicate that the output compare match has occurred Writing to register EMIOS_CADRn stores the value in register A2 and...

Page 608: ...de measures the width of a positive or negative pulse by capturing the leading edge on register B1 and the trailing edge on register A2 Successive captures are done on consecutive edges of opposite po...

Page 609: ...reading EMIOS_CADRn forces B1 to be updated with the content of register A1 At the same time transfers between B2 and B1 are disabled until the next read of the EMIOS_CBDRn register Reading EMIOS_CBD...

Page 610: ...s read EMIOS_CBDRn before reading EMIOS_CADRn If B1 register updates are blocked after an EMIOS_CADRn read a second EMIOS_CBDRn read is required to release B1 register updates 16 4 4 4 5 Input Period...

Page 611: ...Registers EMIOS_CADRn and EMIOS_CBDRn return the values in register A2 and B1 respectively To allow coherent data reading EMIOS_CADRn forces A1 content to be transferred to the B1 register and disabl...

Page 612: ...n the DAOC mode is first selected coming from GPIO mode both comparators are disabled Comparators A and B are enabled by updating registers A1 and B1 respectively and remain enabled until a match occu...

Page 613: ...ith the same value the unified channel behaves as if a single match on comparator B had occurred that is the output flip flop is set to the complement of EDPOL bit and the FLAG bit is set Figure 16 23...

Page 614: ...transfers are disabled until the next read of the EMIOS_CBDRn register Reading the EMIOS_CBDRn register re enables transfers from B2 to B1 to take effect at the next transfer event as described above...

Page 615: ...16 26 show how the unified channel can be used for continuous and single shot pulse edge accumulation mode Figure 16 25 Pulse Edge Accumulation Continuous Mode Example Selected counter bus 0x000090 0x...

Page 616: ...for the time window After writing to register A1 when a match occur between comparator A and the selected timebase the internal counter is cleared and it is ready to start counting input events When...

Page 617: ...ressed by the alternate address EMIOS_ALTAn For single shot operation MODE 6 set the next match between comparator A and the selected time base has no effect until a new write to register A is perform...

Page 618: ...and phase_B encoders When operating with count and direction encoder MODE 6 cleared UCn input pin must be connected to the direction signal and UC n 1 input pin must be connected to the count signal o...

Page 619: ...phase_A and phase_B encoders respectively Figure 16 29 Quadrature Decode Mode Example with Count and Direction Encoder Figure 16 30 Quadrature Decode Mode Example with Phase_A and Phase_B Encoder Dir...

Page 620: ...the input signal has the same polarity of EDPOL bit in EMIOS_CCRn and does not count otherwise When a match occurs in comparator B the internal counter is disabled regardless of the input signal polar...

Page 621: ...counter Up down counter no change in counter direction upon match of input counter and register B1 internal clock source 0b0010101 Modulus counter Up down counter no change in counter direction upon...

Page 622: ...nter and register A1 sets the FLAG and clears the internal counter When in up down count mode a match between the internal counter and register A1 sets the FLAG and changes the counter direction from...

Page 623: ...00 EMIOS_CCNTRn FLAG set event MODE 4 0 A1 match A1 match A1 value1 Notes 1 Writing EMIOS_An writes to A2 A2 value transferred to A1 according to OUn bit Time 0x000000 A1 match A1 match 0x000200 0x000...

Page 624: ...any time the FORCMA and FORCMB bits allow the software to force the output flip flop to the level corresponding to a match on A or B respectively Also FORCMB clears the internal counter The FLAG bit...

Page 625: ...return to the previous duty cycle restore register A with its former value NOTE Updates to the A register always occur immediately If next period update is selected via the mode 6 bit only the B regis...

Page 626: ...5 OPWFM with Next Period Update A1 value1 B1 value B2 value2 0x001000 0x000900 Output flip flop A1 match A1 match Time 0x000000 B1 match 0x000200 0x000200 0x001000 0x000900 0x000200 Write to A2 and B2...

Page 627: ...16 25 has additional illustrative examples Table 16 25 Examples of Output Waveforms EDPOL Duty Cycle A decimal B decimal Waveform 0 Active high output 0 1000 1000 25 250 1000 50 500 1000 75 750 1000...

Page 628: ...clears the internal counter and switches the selected time base to the internal counter When a match occurs between register B1 and the selected time base the output flip flop is set to the value of t...

Page 629: ...rs A1 and B1 must be set to the same value When a simultaneous match occurs between the selected time base and registers A1 and B1 the output flip flop is set at every period to the value of EDPOL bit...

Page 630: ...Dead time Insertion Output flip flop A1 match A1 match Time 0x000000 0x000303 0x000200 Update to A1 Selected MODE 6 1 counter bus A1 match Notes 1 Writing EMIOS_An writes to A1 2 Writing EMIOS_Bn writ...

Page 631: ...tion FLAG set at match of internal counter and comparator B next period update 0b0100010 Output pulse width modulation FLAG set at match of internal counter and comparator A or comparator B immediate...

Page 632: ...he FORCMA and FORCMB bits allow the software to force the output flip flop to the level corresponding to a match on A or B respectively The FLAG bit is not set by the FORCMA and FORCMB operations If s...

Page 633: ...0900 Update to A1 0xxxxxxx 0x000200 Update to A1 0x001000 Selected MODE 6 0 counter bus A1 match B1 match 0xxxxxxx 0xxxxxxx 0x001000 Notes 1 Writing EMIOS_An writes to A2 2 Writing EMIOS_Bn writes to...

Page 634: ...internal counter starts counting up from its current value to until an A1 match occurs On the next system clock cycle after an A1 match occurs the internal counter is set to one and the counter conti...

Page 635: ...own counter mode The A1 register is updated at the cycle boundary If A2 is written in cycle n this new value is used in cycle n 1 for the next A1 match Flags are generated only at an A1 match if MODE...

Page 636: ...le n to be used in cycle n 1 Thus A1 receives the new value at the next cycle boundary The EMIOS_OUDR n bits can be used to disable the update of A1 register Figure 16 43 eMIOS MCB Mode Example Up Dow...

Page 637: ...ranges from 1 up to B1 value When a match on comparator A occurs the output register is set to the value of EDPOL When a match on comparator B occurs the output register is set to the complement of ED...

Page 638: ...e 16 44 eMIOS OPWFMB Mode Example A1 B1 Match to Output Register Delay 8 1 4 A1 match 5 A1 value 0x000004 A1 match A1 match negative Output flip flop EMIOS_CCNTRn Time B1 match B1 match B1 match negat...

Page 639: ...ame time as the B1 match negative edge from cycle n This allows the use of the A1 match positive edge to mask the B1 match negative edge when they occur at the same time The result is that no transiti...

Page 640: ...A2 instead of A1 for matches if A2 is either 0 or 1 thus allowing matches to be generated even when A1 is being loaded This approach allows a uniform channel operation for any A2 value including 1 an...

Page 641: ...sitions at the following A1 or B1 match In Figure 16 47 it is assumed that the output disable input is enabled and selected for the channel refer to Section 16 3 1 7 eMIOS Channel Control Register EMI...

Page 642: ...e leading or trailing edge A1 and B1 registers are double buffered to allow smooth output signal generation when changing A2 or B2 values asynchronously The selected counter bus for a channel configur...

Page 643: ...to generate matches in cycle n 1 Figure 16 49 eMIOS OPWMCB Mode Example A1 B1 Register Loading The EMIOS_OUDR n bit can be used to disable the A1 and B1 updates thus allowing the loading of these regi...

Page 644: ...ty cycle and dead time values to be changed at simultaneously Figure 16 50 eMIOS PWMCB Mode Example Lead Dead Time Insertion EDPOL 1 Internal Internal counter is Dead time A1 Value A2 Value B1 Value B...

Page 645: ...oth edges when MODE 5 is set If subsequent matches occur on A and B the PWM pulses continue to be generated regardless of the state of the FLAG bit NOTE In OPWMCB mode FORCMA and FORCMB do not have th...

Page 646: ...dence over FORCMA when trailing dead time insertion is selected Duty cycles from 0 to 100 can be generated by setting appropriate A1 and B1 values relative to the period of the external time base Sett...

Page 647: ...channel matches continue to occur in this case thus generating flags When the output disable is negated the channel output flip flop is again controlled by A1 and B1 matches This process is synchrono...

Page 648: ...erated at B1 matches when MODE 5 is cleared or on both A1 and B1 matches when MODE 5 is set If subsequent matches occur on comparators A and B the PWM pulses continue to be generated regardless of the...

Page 649: ...1 and B1 match signals Figure 16 53 shows the value of A1 being set to zero in cycle n 1 In this case the match positive edge is used instead of the negative edge to transition the output flip flop 1...

Page 650: ...using the output flip flop to remain at the EDPOL value thus generating a 0 duty cycle Figure 16 54 eMIOS OPWMB Mode Example 0 Duty Cycle 1 4 A1 match negative A1 value 0x000004 A1 match Output flip f...

Page 651: ...Figure 16 56 if B1 is set to a value lower than 0x000008 it is not possible to achieve 0 duty cycle by only changing A1 register value Since B1 matches have precedence over A1 matches the output flip...

Page 652: ...ese output signals To guarantee that the internal counters of correlated channels are incremented in the same clock cycle the internal prescalers must be set up before enabling the global prescaler If...

Page 653: ...refore the prescaled clock remains high and continuously enables the internal counter EMIOS_CCNTRn Figure 16 57 eMIOS Time Base Generation Block Diagram Figure 16 58 shows the prescaler ratio equal to...

Page 654: ...16 60 Time Base Generation Using the Internal Clock with Clear on Match Start Prescaled clock Internal counter 1 2 0 3 Clock 3 1 2 3 0 1 2 EMIOS_CCNTRn Ratio 3 Match value 3 Initial time base period...

Page 655: ...l modes Added this first sentence to the OPWFM mode In this mode the duty cycle is register A1 1 and the period is register B1 1 Changed register addresses to byte format throughout i e 0x14 0x0014 Ta...

Page 656: ...eTPU engine the host is free to handle higher level operations 17 1 1 MPC5565 eTPU Implementation For more detailed information regarding the eTPU module and compiler refer to the Enhanced Time Proce...

Page 657: ...scriptions are included within this chapter as well as in the Enhanced Time Processing eTPU Reference Manual 17 1 2 Block Diagram Figure 17 1 shows a top level block diagram of a single eTPU engine in...

Page 658: ...service request The service request microcode can send an interrupt to the device core but cannot directly interrupt the core using I O channel events Each channel has a function that consists of a s...

Page 659: ...re driven by a system clock to give absolute time control or by an asyncronous counter such as an angle clock that is tracking the angle of a rotating shaft The eTPU engine consists of the following b...

Page 660: ...a match on TCR1 can capture the value of TCR2 The channels can request service from the microengine due to recognized pin transitions input events or time base matches Every eTPU channel can be config...

Page 661: ...access the SDM space mirrored in an alternate area with parameter sign extension PSE PSE allows accessing 24 bit data as 32 bit sign extended data without using the device s bandwidth to extend the da...

Page 662: ...nnels needing service and grant execution time to each channel The time given to an individual thread for execution or service is called a time slot The duration of a time slot is determined by the nu...

Page 663: ...erations which support jumps calls on channel specific conditions This allows quick and terse channel configuration and control code contributing to reduced service time 17 1 4 7 Debug Interface Nexus...

Page 664: ...export import to from itself An engine cannot import a time base and or angle count if it is in angle mode Event triggered RISC processor microengine 2 stage pipeline implementation fetch and executi...

Page 665: ...kage SDM shared between host core and both eTPU engines supporting channel channel or host channel communication Hardware implementation of four semaphores allows for resource arbitration between chan...

Page 666: ...hoose between them Some features of one mode can be used with features of other modes 17 2 5 eTPU Mode Selection User and user configuration are the production operating modes and differ from each oth...

Page 667: ...t 0 9 ETPUA 0 9 Input Output DSPI C 4 13 None ETPUA 0 9 _ ETPUA 12 21 _ GPIO 114 123 EMIOS 0 9 _ ETPUA 0 9 _ GPIO 179 188 Primary Alternate General purpose I O 10 11 ETPUA 10 11 Input Output DSPI C 14...

Page 668: ...utput disable signal is active all the eight channels assigned to the disable signal that have their ODIS bits set to one in ETPU_CnCR register have their outputs forced to the opposite of the value s...

Page 669: ...x0000_002F eTPU A time base registers Base 0x0000_0030 Base 0x0000_01FF Reserved Base 0x0000_0200 Base 0x0000_02FF eTPU A global channel registers Base 0x0000_0300 Base 0x0000_03FF Reserved Base 0x000...

Page 670: ...figuration register 32 Base 0x0000_001C Reserved Base 0x0000_0020 ETPU_TBCR_A eTPU A time base configuration register 32 Base 0x0000_0024 ETPU_TB1R_A eTPU A time base 1 32 Base 0x0000_0028 ETPU_TB2R_A...

Page 671: ...ter 32 Base 0x0000_040C Reserved Base 0x0000_0410 ETPU_C1CR_A eTPU A channel 1 configuration register 32 Base 0x0000_0414 ETPU_C1SCR_A eTPU A channel 1 status and control register 32 Base 0x0000_0418...

Page 672: ...t accesses Address Base 0x0000_0000 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 MGEA MGEB ILFA 0 0 0 0 SCMSIZE W GEC Reset 0 0 0 0 0 0 0 0 0 0 0 SCMSIZE 16 17 18 19 20 21 22 23 24 25 26...

Page 673: ...dicate that the calculated signature does not match the expected value at the end of a MISC iteration For more details refer to the eTPU Reference Manual for more details 0 Signature mismatch not dete...

Page 674: ...ddress Base 0x0000_0004 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R STS CTBASE PBBASE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R PWID TH PARM0 WR...

Page 675: ...r 0 This field in concatenation with CTBASE 3 0 determine the address offset from the SDM base address of the parameter which is the destination or source defined by WR of the coherent transfer The SD...

Page 676: ...ction Global Exception and ends the thread 17 4 3 5 eTPU Engine Configuration Register ETPU_ECR Each engine has its own ETPU_ECR The ETPU_ECR holds configuration and status fields that are programmed...

Page 677: ...base registers For more information on channel registers refer to Section 17 4 6 Channel Configuration and Control Registers After MDIS is set even before STF asserts data read from the channel regist...

Page 678: ...s three digital filtering modes for the channels which provide programmable trade off between signal latency and noise immunity For more information on filtering refer to the eTPU Reference Manual Cha...

Page 679: ...icrocode entry table for the eTPU functions in SCM More information about entry points is located in the eTPU Reference Manual The following table shows the entry table base address options 1 The time...

Page 680: ...register configures several time base options Address Base 0x0000_0020 eTPU A Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R TCR2CTL TCRCF 0 AM 0 0 0 TCR2P W Reset 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0...

Page 681: ...so whether the TCRCLK digital filter works in integrator mode or two sample mode The following table describes TCRCLK filter clock mode For more information refer to the eTPU Reference Manual TCR2CTL...

Page 682: ...nternal Timebase input or TCRCLK filtered input This field has no effect on TCCR2 in Angle Mode For more information on TCR2 refer to the eTPU Reference Manual 16 23 TCR1CTL TCR1 clock gate control Pa...

Page 683: ...the configuration set in ETPU_REDCR For more information refer to the eTPU Reference Manual Address Base 0x0000_0024 eTPU A Access R O 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 TCR1 W R...

Page 684: ...when in angle mode and STAC interface configurations set in registers ETPU_TBCR and ETPU_REDCR For more information on time bases refer to the eTPU Reference Manual Address Base 0x0000_0028 eTPU A Ac...

Page 685: ...s disabled 1 Server client operation for resource 1 is enabled 1 RSC1 TCR1 resource server client assignment Selects the eTPU data resource assignment to be used as a server or client RSC1 selects the...

Page 686: ...t assignment Selects the eTPU data resource assignment to be used as a server or client RSC2 selects the functionality of TCR2 For server mode external plugging determines the unique server address as...

Page 687: ...still have their status bits DTRSn cleared by writing a 1 to the appropriate field Address Base 0x0000_0200 eTPU A Access R W1c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CIS31 CIS30 CIS29 CIS28 CIS27 CI...

Page 688: ...9 10 11 12 13 14 15 R DTRS 31 DTRS 30 DTRS 29 DTRS 28 DTRS 27 DTRS 26 DTRS 25 DTRS 24 DTRS 23 DTRS 22 DTRS 21 DTRS 20 DTRS 19 DTRS 18 DTRS 17 DTRS 16 W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c...

Page 689: ...30 CIOS 29 CIOS 28 CIOS 27 CIOS 26 CIOS 25 CIOS 24 CIOS 23 CIOS 22 CIOS 21 CIOS 20 CIOS 19 CIOS 18 CIOS 17 CIOS 16 W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0...

Page 690: ...R OS7 DTR OS6 DTR OS5 DTR OS4 DTR OS3 DTR OS2 DTR OS1 DTR OS0 W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 17 17 eTPU Channel Data Tra...

Page 691: ...tion 0 31 CIEn Channel n interrupt enable Enable the eTPU channels to interrupt the MPC5565 core 0 Interrupt disabled for channel n 1 Interrupt enabled for channel n For details about interrupts refer...

Page 692: ...requesting service the asserted status bit only indicates that one of the requests has been granted NOTE Channel service status does not always reflect decoding of the CHAN register since the CHAN re...

Page 693: ...ister Table 17 22 ETPU_CSSR Field Descriptions Field Description 0 31 SSn Service status n Indicates that channel n is currently being serviced It is updated at the 1st microcycle of a time slot trans...

Page 694: ...U Channel Register Map Address Registers Structure Base 0x0000_0400 eTPU A channel 0 register structure Base 0x0000_0410 eTPU A channel 1 register structure Base 0x0000_0420 eTPU A channel 2 register...

Page 695: ...ntry table condition select Determines the channel condition encoding scheme that selects the entry point to be taken in an entry table The ETCS value has to be compatible with the function chosen for...

Page 696: ...ETPU_CDTRSR and ETPU_CnSCR 18 20 Reserved 21 31 CPBA 0 10 Channel n parameter base address The value of this field multiplied by 8 specifies the SDM parameter base host byte address for channel n 2 pa...

Page 697: ...n on the ETPU_CDTRSR and data transfer refer to Section 17 4 5 2 eTPU Channel Data Transfer Request Status Register ETPU_CDTRSR and the eTPU Reference Manual The core must write 1 to clear DTRS 9 DTRO...

Page 698: ...egister_Base 0x0008 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0...

Page 699: ...In Section 17 1 5 Features changed FROM 32 bit microengine registers and 24 bit resolution ALU with 1 microcycle addition and subtraction absolute value bitwise logical operations on 24 bit 16 bit or...

Page 700: ...d queued analog to digital converter eQADC provides accurate and fast conversions for a wide range of applications The eQADC provides a parallel interface to two on chip analog to digital converters A...

Page 701: ...O underflow occurs when the CFIFO is in the TRIGGERED state and it becomes empty An RFIFO overflow occurs when an RFIFO is full and more data is ready to be moved to the RFIFO by the host CPU or by eD...

Page 702: ...erates control signals for the two on chip ADCs Formats and calibrates conversion result data coming from the on chip ADCs Generates the internal multiplexer control signals and the select signals use...

Page 703: ...he two on chip ADCs Four pairs of differential analog input channels Full duplex synchronous serial interface to an external device A free running clock is provided for use by the external device Supp...

Page 704: ...est is detected there are commands in the ADC that were already under execution these commands are completed but the generated results if any are not sent to the RFIFOs until debug mode is exited Comm...

Page 705: ...atic stable state from which it can recover when returning to normal mode The eQADC then asserts an acknowledge signal indicating that it is static and that the clock input can be stopped In stop mode...

Page 706: ...ng future command transfers from any CFIFO The message of the CFIFO that caused the abort of the previous serial transmission are transmitted only after stop mode exits Command null message transfer t...

Page 707: ...ultiplexed analog input Y I I AN 10 Analog 496 324 AN 11 _ ANZ Single ended analog input 11 External multiplexed analog input Z I I AN 11 Analog 496 324 AN 12 _ MA 0 _ SDS Single ended analog input 12...

Page 708: ...496 324 AN 30 32 Single ended analog input I I AN 30 32 Analog 496 324 AN 33 Single ended analog input I I AN 33 Analog 496 324 AN 34 35 Single ended analog input I I AN 34 35 Analog 496 324 AN 36 Sin...

Page 709: ...er reset of GPI is general purpose input A dash on the left side of the slash denotes that both the input and output buffers for the pin are off A dash on the right side of the slash denotes that ther...

Page 710: ...rupt and eDMA control register 1 16 Base 0x064 EQADC_IDCR2 eQADC interrupt and eDMA control register 2 16 Base 0x066 EQADC_IDCR3 eQADC interrupt and eDMA control register 3 16 Base 0x068 EQADC_IDCR4 e...

Page 711: ...control register 32 Base 0x0B8 EQADC_SSIRDR eQADC synchronous serial interface receive data register 32 Base 0x0BC Base 0x0FC Reserved Base 0x100 Base 0x10C EQADC_CF0Rn eQADC CFIFO0 registers 0 3 32 B...

Page 712: ...7C Reserved Base 0x380 Base 0x38C EQADC_RF2Rn eQADC RFIFO2 registers 0 3 32 Base 0x390 Base 0x3BC Reserved Base 0x3C0 Base 0x3CC EQADC_RF3Rn eQADC RFIFO3 registers 0 3 32 Base 0x3D0 Base 0x3FC Reserve...

Page 713: ...10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 ESSIE 0 DBG W Reset 0 0 0 0 0 0 0 0...

Page 714: ...r level gated trigger The digital filter length field specifies the Address Base 0x008 Access Read Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 NMF W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 715: ...minimum number of system clocks that must be counted by the digital filter counter to recognize a logic state change The count specifies the sample period of the digital filter which is calculated ac...

Page 716: ...9 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W CF_PUSHn Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 18 5 eQADC CFIFO Push Registers 0 5 EQADC_CFPRn Table 18 7 EQADC_CFPRn F...

Page 717: ...Base 0x040 EQADC_RFPR4 Base 0x044 EQADC_RFPR5 Access Read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25...

Page 718: ...n Writing a 1 to CFINVn resets the value of CFCTRn in the EQADC_FISR register refer to Section 18 3 2 8 eQADC FIFO and Interrupt Status Registers 0 5 EQADC_FISRn Writing a 1 to CFINVn also resets the...

Page 719: ...ntinuous scan 0b1010 Low level gated external trigger continuous scan 0b1011 High level gated external trigger continuous scan 0b1100 Falling edge external trigger continuous scan 0b1101 Rising edge e...

Page 720: ...g EOQFn in EQADC_FISRn is asserted Refer to Section 18 3 2 8 eQADC FIFO and Interrupt Status Registers 0 5 EQADC_FISRn 0 Disable end of queue interrupt request 1 Enable end of queue interrupt request...

Page 721: ...mes asserted RFOFn CFUFn and TORFn assuming that all interrupts are enabled Refer to Section 18 4 7 eQADC eDMA Interrupt Request for details 0 Disable overflow interrupt request 1 Enable overflow Inte...

Page 722: ...g transferred by CFIFOn became non coherent Note Non coherency means that a command in the command FIFO was not immediately executed but delayed This may occur if the command is pre empted where a hig...

Page 723: ...with asserted pause bit was transferred from CFIFOn CFIFO in edge trigger mode or CFIFO status changes from the TRIGGERED state due to detection of a closed gate CFIFO in level trigger mode Note In ed...

Page 724: ...details The SSSn bit is set by writing a 1 to the SSEn bit see Section Section 18 3 2 6 eQADC CFIFO Control Registers 0 5 EQADC_CFCRn The eQADC clears the SSSn bit when a command with an asserted EOQ...

Page 725: ...ast one valid entry Note In the interrupt service routine RFDF must be cleared only after the RFIFOn pop register is read Note RFDFn should not be cleared when RFDSn is asserted eDMA requests selected...

Page 726: ...s has no effect Address EQADC_BASE 0x090 EQADC_CFTCR0 EQADC_BASE 0x092 EQADC_CFTCR1 EQADC_BASE 0x094 EQADC_CFTCR2 EQADC_BASE 0x096 EQADC_CFTCR3 EQADC_BASE 0x098 EQADC_CFTCR4 EQADC_BASE 0x09A EQADC_CFT...

Page 727: ...ed 12 16 Reserved 17 20 LCFT0 0 3 Last CFIFO to transfer to ADCn command buffer Holds the CFIFO number of last CFIFO to have initiated a command transfer to ADCn command buffer LCFT0 has the following...

Page 728: ...s initiated 12 16 Reserved 17 20 LCFT1 0 3 Last CFIFO to transfer to ADCn command buffer Holds the CFIFO number of last CFIFO to have initiated a command transfer to ADCn command buffer LCFT1 has the...

Page 729: ...DC_CFSSR2 Table 18 16 EQADC_CFSSR2 Field Descriptions Field Description 0 11 CFSn_ TSSI 0 1 CFIFO Status at Transfer through the eQADC SSI Indicates the CFIFOn status at the time a serial transmission...

Page 730: ..._LCFTSSI is a copy of the corresponding TC_CFn in EQADC_CFTCRn see Section 18 3 2 9 eQADC CFIFO Transfer Counter Registers 0 5 EQADC_CFTCRn captured at the time a command transfer to an external comma...

Page 731: ...nsfer of the last entry of the user defined command queue in single scan mode Reserved 0b01 Not applicable WAITING FOR TRIGGER 0b10 CFIFO mode is modified to continuous scan edge or level trigger mode...

Page 732: ...are disabled Refer to EQADC_MCR ESSIE field in Section 18 3 2 1 eQADC Module Configuration Register EQADC_MCR 24 27 Reserved 28 31 BR 0 3 Baud rate Selects system clock divide factor as shown in Tabl...

Page 733: ...0 1 1 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R R_DATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 18 16 eQADC SSI Receive Data Register EQADC_SSIRDR Table 18 22 EQADC_SSIRDR Field Desc...

Page 734: ...Base 0x180 CF2R0 Base 0x184 CF2R1 Base 0x188 CF2R2 Base 0x18C CF2R3 Access Read CFIFO3 Base 0x1C0 CF3R0 Base 0x1C4 CF3R1 Base 0x1C8 CF3R2 Base 0x1CC CF3R3 CFIFO4 Base 0x200 CF4R0 Base 0x204 CF4R1 Bas...

Page 735: ...0 RF2R0 Base 0x384 RF2R1 Base 0x388 RF2R2 Base 0x38C RF2R3 Access Read RFIFO3 Base 0x3C0 RF3R0 Base 0x3C4 RF3R1 Base 0x3C8 RF3R2 Base 0x3CC RF3R3 RFIFO4 Base 0x400 RF4R0 Base 0x404 RF4R1 Base 0x408 RF...

Page 736: ...nt to the ADC0 command buffer Registers ADC1_CR ADC1_GCCR and ADC1_OCCR can only be accessed by configuration commands sent to the ADC1 command buffer Registers ADC_TSCR and ADC_TBCR can be accessed b...

Page 737: ...1 This register is also accessible by configuration commands sent to the ADC0 command buffer Write Read 0x03 ADC Time Base Counter Register ADC_TBCR 1 Write Read 0x04 ADC1 Gain Calibration Constant Re...

Page 738: ...exer inputs Refer to Section 18 4 6 Internal External Multiplexing for a detailed description about how ADCn_EMUX affects channel number decoding 0 External multiplexer disabled no external multiplexe...

Page 739: ...s sent to ADC0 or to ADC1 A data write to ADC_TSCR using a configuration command sent to ADC0 writes to the same memory location as a write using a configuration command sent to ADC1 NOTE Simultaneous...

Page 740: ...12 15 TBC_ CLK_PS 0 3 Time base counter clock prescaler Contains the system clock divide factor for the time base counter It controls the accuracy of the time stamp The prescaler is disabled when TBC...

Page 741: ...es from ADC0 and ADC1 to ADC_TBCR are not allowed 18 3 3 4 ADCn Gain Calibration Constant Registers ADC0_GCCR and ADC1_GCCR The ADCn_GCCR contains the gain calibration constant used to fine tune the A...

Page 742: ...alibration Constant Registers ADCn_GCCR Table 18 32 ADCn_GCCR Field Descriptions Field Description 0 Reserved 1 15 GCCn 0 14 ADCn gain calibration constant Contains the gain calibration constant used...

Page 743: ...e of operation of the CFIFO The eQADC can also in parallel and independently of the CFIFOs receive data from the on chip ADCs or from off chip external device into multiple RFIFOs Result data is moved...

Page 744: ...ult data flows inside the eQADC system Results generated on the on chip ADCs are formatted into result messages inside the result format and calibration submodule Results returning from the external d...

Page 745: ...ol Unit To ADCs eQADC SSI eQADC ADC eQADC SSI External Device Logic Buffers DMA Transaction Done Signals Host CPU or DMAC DMA or Interrupt Requests NOTES n 0 1 2 3 4 5 ADC Command CFIFO Header Command...

Page 746: ...ecides to which external command buffer a command should go by decoding the upper bit BN bit of the ADC command see Section Command Message Format for External Device Operation An external device that...

Page 747: ...sult The FIFO control unit decodes the information contained in the RFIFO header to determine the RFIFO to which the ADC result should be sent An ADC result is always 16 bits long 18 4 1 2 1 Message F...

Page 748: ...us changes as if only the EOQ bit were asserted 1 PAUSE Pause Allows software to create sub queues within a command queue When the eQADC completes the transfer of a command with an asserted pause bit...

Page 749: ...ture for details 0 Return conversion result only 1 Return conversion time stamp after the conversion result 15 FMT Conversion data format FMT specifies to the eQADC how to format the 12 bit conversion...

Page 750: ...mand queue to indicate to the eQADC that a scan of the queue is completed EOQ instructs the eQADC to reset its current CFIFO transfer counter value TC_CF to 0 Depending on the CFIFO mode of operation...

Page 751: ...pending on the EB bit setting 0 Message stored in buffer 0 1 Message stored in buffer 1 7 R W Read write A negated R W indicates a write configuration command 0 Write 1 Read 8 15 ADC_ REGISTER _HIGH_...

Page 752: ...ADC completes the transfer of a command with an asserted pause bit the CFIFO enters the WAITING FOR TRIGGER state Refer to Section 18 4 3 6 1 CFIFO Operation Status for a description of the state tran...

Page 753: ...ing a 2 bit left shift on the 12 bit data received from the ADC When the CAL bit is asserted 8 11 MESSAGE _TAG 0 3 MESSAGE_TAG field Allows the eQADC to separate returning results into different RFIFO...

Page 754: ...XT CONVERSION_RESULT With inverted msb bit 0 0 ADC Result Figure 18 29 ADC Result Format when FMT 1 Right Justified Signed On Chip ADC Operation Table 18 37 ADC Result Format when FMT 1 Field Descript...

Page 755: ...unit external device to which external command buffer the corresponding command should be sent The remaining 25 bits can be anything decodable by the external device Only the ADC command portion of a...

Page 756: ...escription of the state transitions The pause bit is only valid when CFIFO operation mode is configured to single or continuous scan edge trigger mode 0 Do not enter WAITING FOR TRIGGER state after tr...

Page 757: ...30 31 ADC_RESULT ADC Result Figure 18 32 Result Message Format for External Device Operation Table 18 41 Result Message Format for External Device Operation Field Description 6 7 Reserved 8 11 MESSAG...

Page 758: ...nsfers a null message it directly shifts out the 26 bit data content inside the Section 18 3 2 2 eQADC Null Message Send Format Register EQADC_NMSFR The register must be programmed with the null messa...

Page 759: ...s 18 4 3 1 CFIFO Basic Functionality There are six prioritized CFIFOs located in the eQADC Each CFIFO is four entries deep and each CFIFO entry is 32 bits long A CFIFO serves as a temporary storage lo...

Page 760: ...data pointer and CFCTR in the same register provides the number of entries stored in the CFIFO Using TNXTPTR and CFCTR the absolute addresses for the entries indicated by the transfer next data point...

Page 761: ...ounter value and does not overwrite any entry in CFIFOn Figure 18 35 CFIFO Diagram The detailed behavior of the push next data pointer and transfer next data pointer is described in the example shown...

Page 762: ...mmand buffer that is not full and it is the highest priority triggered CFIFO sending commands to that buffer First In Transfer Next Data Pointer Last In Push Next Data Pointer CFIFOn Transfer Next Dat...

Page 763: ...s are not considered for prioritization No data from these CFIFOs is sent to the on chip ADCs or the external command buffers and lower priority CFIFOs are not stopped from transferring commands Whene...

Page 764: ...tly transmitting null message is not shifted out The command from the CFIFO is then written into eQADC SSI transmit buffer allowing for a new serial transmission to initiate In case a command is being...

Page 765: ...oad that command and start its transmission However if the previously scheduled data was a command no rescheduling occurs and the next transmission starts without delays If a CFIFO becomes triggered w...

Page 766: ...g counter is cleared and restarted each time the signal transitions between logic levels When the corresponding counter matches the value specified by the digital filter length field in Section 18 3 2...

Page 767: ...is scanned multiple times The eQADC also supports different triggering mechanisms for each scan mode The eQADC does not transfer commands from a CFIFO until the CFIFO is triggered The combination of...

Page 768: ...nvalidated by writing a 1 to the CFINVn bit see Section 18 3 2 6 eQADC CFIFO Control Registers 0 5 EQADC_CFCRn Certify that CFS has changed to IDLE before setting CFINVn The TC_CFn value also is not r...

Page 769: ...ge triggered mode is selected for a CFIFO an appropriate edge on the associated trigger signal causes the CFIFO to become triggered For example if rising edge trigger mode is selected the CFIFO become...

Page 770: ...e EQADC_CFCRn SSE see Section 18 3 2 6 eQADC CFIFO Control Registers 0 5 EQADC_CFCRn does not have any effect Continuous Scan Software Trigger When a CFIFO is programmed to continuous scan software tr...

Page 771: ..._CF counter is updated the PF flag is asserted and the CFIFO status is changed to waiting for trigger Command transfers restart as the gate opens If the gate closes and opens during the same serial tr...

Page 772: ...n Level No Gate is opened No No The eQADC also stops transfers from the CFIFO when CFIFO status changes from triggered due to the detection of a closed gate 5 1 Refer to Section 18 4 3 6 2 Command Que...

Page 773: ...IGGER 0b10 CFIFO mode is programmed to continuous scan edge or level trigger mode OR CFIFO mode is programmed to single scan edge or level trigger mode and SSS is asserted OR CFIFO mode is programmed...

Page 774: ...ied to disabled OR CFIFO in single scan level trigger mode and the gate closes while no commands are being transferred from the CFIFO and CFIFO mode is not modified to disabled OR CFIFO in single scan...

Page 775: ...egisters 0 5 EQADC_FISRn Section 18 3 2 8 eQADC FIFO and Interrupt Status Registers 0 5 EQADC_FISRn Section 18 4 1 2 Message Format in eQADC for information on command message formats In level trigger...

Page 776: ...6 5 Command Sequence Non Coherency Detection The eQADC provides a mechanism to indicate if a command sequence has been completely executed without interruptions A command sequence is defined as a grou...

Page 777: ...e commands are transferred by a CFIFO configured for edge trigger mode and the command transfers are never interrupted the eQADC would check for non coherency of two command sequences one formed by co...

Page 778: ...command buffer is considered empty when the corresponding BUSY field in the last result message received from external device is encoded as Send available commands buffer is empty Refer to Section Res...

Page 779: ...ence After command transfers restart or continue the non coherency hardware operate as if the command sequence started from that point Figure 18 45 depicts how the non coherency hardware operates when...

Page 780: ...mmands to be sent to ADC1 and both are not triggered a CFIFO5 CF5_ADC1_CM3 3 CF5_ADC1_CM2 2 Sent 1 Sent 0 TNXTPTR ADC1 CF5_ADC1_CM1 1 CF5_ADC1_CM0 0 CFIFO5 becomes triggered and transfers CFIFO0 CF0_A...

Page 781: ...external CFIFO0 CF0_2_CM3 3 CF0_2_CM2 2 Sent 1 Sent 0 TNXTPTR command buffer 2 CFIFO5 cannot send commands to external command buffer 3 because the eQADC SSI is b Command Buffer 3 CF5_3_CM1 1 Empty 0...

Page 782: ...op Registers 0 5 EQADC_RFPRn to retrieve data from the RFIFO NOTE Reading a word halfword or any bytes from EQADC_RFPRn pops an entry from RFIFOn and the RFCTRn field is decremented by 1 The eDMA cont...

Page 783: ...When a new message arrives and RFIFOn is not full the eQADC copies its contents into the entry pointed by receive next data pointer The RFIFO counter EQADC_FISRn RFCTRn see Section 18 3 2 8 eQADC FIF...

Page 784: ...he actual hardware implementation has only four entries In this example RFIFOn with 16 entries is shown in sequence after popping or receiving entries Pop Next Data Entry 1 Data Entry 2 Control Signal...

Page 785: ...FIFO number or Ignores the data in case of a null or reserved for customer use MESSAGE_TAG First In Pop Next Data Pointer Last In Receive Next Data Pointer RFIFOn Pop Next Data Pointer Receive Next Da...

Page 786: ...negated After the enable bit of an ADC is asserted clock input is started and the bias generator circuit is turned on When the enable bits of both ADCs are negated the bias circuit generator is stoppe...

Page 787: ...differential conversions and 14 for single ended conversions The maximum conversion speed is achieved when the ADC Clock frequency is set to its maximum 12Mhz and the number of sampling cycles set to...

Page 788: ...4 N A N A N A 0b00010 6 N A N A N A 0b00011 8 N A N A N A 0b00100 10 12 0 800 750 0b00101 12 10 0 667 625 0b00110 14 8 57 571 536 0b00111 16 7 5 500 469 0b01000 18 6 67 444 417 0b01001 20 6 0 400 375...

Page 789: ...uency it is incremented The time stamps are returned regardless of whether the time base counter is enabled or disabled The time base counter can be reset by writing 0x0000 to the ADC_TBCR Section 18...

Page 790: ...is not calibrated it bypasses the calibration hardware and is directly sent to the appropriate RFIFO 18 4 5 4 2 MAC Unit and Operand Data Format The MAC unit diagram is shown in Figure 18 49 Each on c...

Page 791: ...n Calibration Constant Format Table 18 48 Gain Calibration Constant Format Field Descriptions Field Description 0 Reserved 1 GCC_I NT 0 Integer part of the gain calibration constant for ADCn GCC_INT i...

Page 792: ...ve conversion commands are pipelined and their execution can start while in ENTRY0 This is explained below A D conversion accuracy can be affected by the settling time of the input channel multiplexer...

Page 793: ...MA0 MA1 Configuration Registers EMUX0 EMUX1 Entry1 LST0 Entry0 ADC0 Buffer Entry1 LST1 Entry0 ADC1 Buffer Register Data 0 1 CHANNEL_NUMBER0 CHANNEL_NUMBER1 MESSAGE_TAG1 FMT1 CAL1 MESSAGE_TAG0 FMT0 CA...

Page 794: ...erminals of the ADC The differential conversions can only be initiated on four channels DAN0 DAN1 DAN2 and DAN3 Refer to Table 18 51 and Figure 18 52 for the channel numbers used to select differentia...

Page 795: ...rsions are not allowed Also when one ADC is performing a differential conversion on a pair of pins the other ADC must not access either of these two pins as single ended channels Input Pins Channel Nu...

Page 796: ...mum configuration of four external multiplexer chips connected to the eQADC The external multiplexer chip selects one of eight analog inputs and connects it to a single analog Table 18 52 Multiplexed...

Page 797: ...ANW ANX ANY and ANZ with MA0 being the most significant bit Refer to Table 18 53 When the external multiplexed mode is selected for either ADC the eQADC automatically creates the MA output signals fr...

Page 798: ...s are described in Section 18 3 2 7 eQADC Interrupt and eDMA Control Registers 0 5 EQADC_IDCRn and the interrupt flag bits are described in Section 18 3 2 8 eQADC FIFO and Interrupt Status Registers 0...

Page 799: ...r CFFFn bit by writing a 1 to the bit Result FIFO Overflow Interrupt2 2 Apart from generating an independent interrupt request for when a RFIFO overflow interrupt a CFIFO underflow interrupt and a CFI...

Page 800: ...ill DMA Request RFDEn RFDFn RFDSn RFIFO Drain DMA Request DMA Request Generation Logic CFFEn CFFFn CFFSn CFIFO Fill Interrupt Request NCIEn NCFn Non Coherency Interrupt Request PIEn PFn Pause Interrup...

Page 801: ...ing the EQADC_MCR ESSIE see Section 18 3 2 1 eQADC Module Configuration Register EQADC_MCR When enabled the eQADC SSI can be optionally capable of starting serial transmissions When serial transmissio...

Page 802: ...the positive edge of FCK and latches incoming data on the next positive edge of FCK Slave drives data on the positive edge of FCK and latches incoming data on the negative edge of FCK Master initiate...

Page 803: ...e of the FCK as a clock on the slave device 18 4 8 1 1 Abort Feature The master indicates it is aborting the current transfer by negating SDS before the whole data frame has being shifted out that is...

Page 804: ...Interface Protocol Timing NOTE tMDT Minimum tDT is programmable and defined in Section 18 3 2 12 eQADC SSI Control Register EQADC_SSICR FCK SDS Master Sample Input SDO 1 End Transmission tDT Slave Sa...

Page 805: ...positive edge of FCK Slave drives second bit due to detection of an asserted SDS on the negative edge of FCK 1 FCK SDS Slave Sample Input tDT Master s SDI 26 25 1 2 3 End Transmission Begin Transmiss...

Page 806: ...in Figure 18 60 To begin an analog to digital conversion a differential input is passed into the analog RSD stage The signal is passed through the RSD stage and then from the RSD stage output back to...

Page 807: ...t the end of an entire AD conversion cycle the RSD adder uses these collected values to calculate the 12 bit digital output Figure 18 62 shows the transfer function for the RSD stage Note how the digi...

Page 808: ...ultiple user command queues Table 18 56 describes how each queue can be used for a different application Also documented in this section are general guidelines on how to initialize the on chip ADCs an...

Page 809: ...nable the eQADC SSI to start serial transmissions 5 Configure the eDMA to transfer data from Queue0 to CFIFO0 in the eQADC 6 Configure Section 18 3 2 7 eQADC Interrupt and eDMA Control Registers 0 5 E...

Page 810: ...ues in the RAM by the eDMA NOTE There is no fixed relationship between CFIFOs and RFIFOs with the same number The results of commands being transferred through CFIFO1 can be returned to any RFIFO rega...

Page 811: ...ueue 1 Table 18 57 Example of Command Queue Commands1 1 Fields LST TSR FMT and CHANNEL_NUMBER are not shown for clarity Refer to Section Conversion Command Message Format for On Chip ADC Operation for...

Page 812: ...DC CFIFO Control Registers 0 5 EQADC_CFCRn Step Four Command transfer to ADCs and result data reception When an external rising edge event occurs for CFIFO1 the eQADC automatically begins transferring...

Page 813: ...le scan mode Refer to Chapter 9 Enhanced Direct Memory Access eDMA for details about how this functionality is supported 18 5 2 2 Receive Queue RFIFO Transfers In transfers involving receive queues an...

Page 814: ...101 Refer to Section 18 3 2 4 eQADC CFIFO Push Registers 0 5 EQADC_CFPRn 4 Up to 4 commands can be queued in CFIFO5 Check the CFCTR5 status in EQADC_FISR5 before pushing another command to avoid overf...

Page 815: ...EQADC_CFCRn CFINVn see Section 18 3 2 6 eQADC CFIFO Control Registers 0 5 EQADC_CFCRn to invalidate the entries of CFIFOn 7 Configure the eDMA to respond to eDMA requests generated by CFFFn and RFDFn...

Page 816: ...Command 0 No Results 0x0000 CQueue0 Read Command 1 Results to RQueue0 0x0004 CQueue0 Conversion Command 2 Results to RQueue0 0x0008 CQueue0 Conversion Command 3 Results to RQueue1 0x000C CQueue0 Conv...

Page 817: ...tically calibrates the results according to Equation 18 1 of every conversion command that has its CAL bit asserted using the GCC and OCC values stored in the ADC calibration registers 18 5 6 1 MAC Co...

Page 818: ...re using Equation 18 4 and Equation 18 5 the gain and offset calibration constants are GCC 12288 4096 11592 3798 1 05106492 1 051025391 0x4344 OCC 12288 1 05106492 11592 2 102 06 102 0x0066 Table 18 5...

Page 819: ...onality This section targets users familiar with terminology in QADC Figure 18 69 is an overview of a QADC Figure 18 69 QADC Overview 4 Ideal Transfer Curve 0 Shifted Transfer Curve ADC Transfer Curve...

Page 820: ...SSI is implemented to transmit and receive data between the eQADC and the external device Because there are only FIFOs inside the eQADC much of the terminology or use of the register names register c...

Page 821: ...ng a pause bit in the CCW pauses the queue execution In the eQADC detecting a pause bit in the command pauses command transfers from a CFIFO Queue Operation Mode MQn CFIFO Operation Mode MODEn The eQA...

Page 822: ...History Table 18 61 Changes Between MPC5565RM Revisions 0 1 and 1 Removed section 9 2 Detailed Signals from this chapter because this information is contained in the Signals chapter of the Reference...

Page 823: ...Enhanced Queued Analog to Digital Converter eQADC MPC5565 Microcontroller Reference Manual Rev 1 0 18 124 Freescale Semiconductor...

Page 824: ...PI which provides a synchronous serial bus for communication between the MCU and an external peripheral device Microcontroller chips in the MPC55xx family implement different DSPI modules Some impleme...

Page 825: ...data may be used to trigger external interrupt requests through DSPI deserialized output connections to the SIU The channels and register content are transmitted using an SPI protocol There are three...

Page 826: ...SPI frames giving priority to SPI frames For queued operations the SPI queues reside in internal SRAM which is external to the DSPI Data transfers between the queues and the DSPI FIFOs are accomplish...

Page 827: ...IFO is not empty RFDF Six interrupt conditions End of queue reached EOQF TX FIFO is not full TFFF Transfer of current frame complete TCF RX FIFO is not empty RFDF FIFO overrun attempt to transmit with...

Page 828: ...mode allows the DSPI to initiate and control serial communication In this mode the SCK PCSn and SOUT signals are controlled by the DSPI and configured as outputs For more information refer to Section...

Page 829: ...ve select input signal that allows an SPI master to select the DSPI as the target for transmission PCSx 0 SS must be configured as input and pulled high If the internal pullup is being used then the a...

Page 830: ...Sx 5 is a peripheral chip select output signal When the DSPI is in master mode and PCSSE bit in the DSPIx_MCR is cleared the PCSx 5 signal is used to select the slave device that receives the current...

Page 831: ...ck and transfer attributes register 4 32 Base 0x0020 DSPIx_CTAR5 DSPI clock and transfer attributes register 5 32 Base 0x0024 DSPIx_CTAR6 DSPI clock and transfer attributes register 6 32 Base 0x0028 D...

Page 832: ...comparison register 32 Base 0x00CC DSPIx_DDR DSPI DSI deserialization data register 32 Address Base 0x0000 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R MSTR CONT_ SCKE DCONF FRZ MTFE PCS SE RO O...

Page 833: ...d as the Peripheral chip select 5 signal 1 PCSx 5 PCSS is used as an active low PCS strobe signal 7 ROOE Receive FIFO overflow overwrite enable Enables an RX FIFO overflow condition to ignore the inco...

Page 834: ...ion 19 4 3 3 FIFO Disable Operation for details 0 RX FIFO is enabled 1 RX FIFO is disabled 20 CLR_TXF Clear TX FIFO Flushes the TX FIFO Write a 1 to the CLR_TXF bit to clear the TX FIFO counter The CL...

Page 835: ...ction 19 5 4 MPC5xx QSPI Compatibility with the DSPI for a discussion on DSPI QSPI compatibility At the initiation of an SPI or DSI transfer control logic selects the DSPIx_CTAR that contains the tran...

Page 836: ...e information on the DSPIx_DSICR refer to Section 19 3 2 10 DSPI DSI Configuration Register DSPIx_DSICR When the DSPI is configured as a DSI bus slave the DSPIx_CTAR1 register is used In CSI configura...

Page 837: ...ed in the following table Refer to the BR field below and Section 19 4 6 1 Baud Rate Generator for details on how to compute the baud rate If the overall baud rate is divided by two or divided by thre...

Page 838: ...evices the devices must have identical clock phase settings 0 Data is captured on the leading edge of SCKx and changed on the following edge 1 Data is changed on the leading edge of SCKx and captured...

Page 839: ...ble 19 5 details how to compute the delay after transfer 14 15 PBR 0 1 Baud rate prescaler Selects the prescaler value for the baud rate Use in master mode only The baud rate is the frequency of the s...

Page 840: ...is the delay between the last edge of SCKx and the negation of PCSx The following table lists the scaler values The after SCKx delay is a multiple of the system clock period and it is computed using t...

Page 841: ...of the next frame The following table lists the scaler values The delay after transfer is a multiple of the system clock period It is computed using the following equation Note Refer to Section 19 4...

Page 842: ...f the SCK The following table lists the baud rate scaler values The baud rate is computed using the following equation Note Refer to Section 19 4 6 1 Baud Rate Generator for more details Address Base...

Page 843: ...details The EOQF bit is cleared by writing 1 to it When the EOQF bit is set the TXRXS bit is automatically cleared 0 EOQ is not set in the executing command 1 EOQ bit is set in the executing SPI comma...

Page 844: ...ansferred to the shift register 20 23 TXNXTPTR 0 3 Transmit next pointer Indicates which TX FIFO entry is transmitted during the next transfer The TXNXTPTR field is updated every time SPI data is tran...

Page 845: ...le Enables the TFFF flag in the DSPIx_SR to generate a request The TFFF_DIRS bit selects between generating an interrupt request or a DMA requests 0 TFFF interrupt requests or DMA requests are disable...

Page 846: ...IFO drain DMA or interrupt request select Selects between generating a DMA request or an interrupt request When the RFDF flag bit in the DSPIx_SR is set and the RFDF_RE bit in the DSPIx_RSER is set th...

Page 847: ...table shows how the CTAS values map to the DSPIx_CTARs There are eight DSPIx_CTARs in the device DSPI implementation Note Use in SPI master mode only 4 EOQ End of queue Provides a means for host softw...

Page 848: ...re read DSPIx_POPR only when you need the data For compatibility configure the TLB MMU table entry for DSPIx_POPR as guarded 10 15 PCSx Peripheral chip select x Selects which PCSx signals are asserted...

Page 849: ...eld Descriptions Field Description 0 15 Reserved must be cleared 16 31 RXDATA 0 15 Received data The RXDATA field contains the SPI data from the RX FIFO entry pointed to by the pop next data pointer P...

Page 850: ...he RX FIFO that is DSPIx_RXFR0 DSPIx_RXFR3 are used The following table describes the field in the DSPI receive FIFO register Address Base 0x007C DSPIx_RXFR0 Base 0x0080 DSPIx_RXFR1 Base 0x0084 DSPIx_...

Page 851: ...ion 0 Multiple transfer operation disabled 1 Multiple transfer operation enabled 1 Reserved 2 7 MTOCNT 0 5 Multiple transfer operation count Selects number of bits to be shifted out during a transfer...

Page 852: ...enable Enables the PCSx signals to remain asserted between transfers The DCONT bit only affects the PCS signals in DSI master mode Refer to Section 19 4 7 5 Continuous Selection Format for details 0...

Page 853: ...Data Register DSPIx_ASDR The DSPIx_ASDR allows the host software to write data to be serialized When the TXSS bit in the DSPIx_DSICR is set the data in the DSPIx_ASDR is the source of the serialized d...

Page 854: ...14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R ASER_DATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19 14 DSPI D...

Page 855: ...DSPI can also be used to reduce the number of pins required for I O by serializing and deserializing up to 16 parallel input output signals from the eTPU and eMIOS All communications are through an SP...

Page 856: ...r SPI dictates which CTAR the CSI configuration uses Refer to Section 19 3 2 3 DSPI Clock and Transfer Attributes Registers 0 7 DSPIx_CTARn for information on DSPIx_CTAR fields The 16 bit shift regist...

Page 857: ...master mode transfer attributes are controlled by the DSPIx_DSCIR A detailed description of the DSPIx_DSCIR is located in Section 19 3 2 10 DSPI DSI Configuration Register DSPIx_DSICR The DSISCTAS fie...

Page 858: ...the FRZ bit in the DSPIx_MCR is set the DSPI stops all serial transfers and enters a stopped state If the MCU enters debug mode while the FRZ bit is cleared the DSPI behavior is unaffected and remains...

Page 859: ...conditions are described in Section 19 4 9 Interrupts DMA Requests The SPI configuration supports two module specific modes master mode and slave mode The FIFO operations are similar for the master mo...

Page 860: ...tware transmit data and commands are written to the DSPIx_PUSHR and received data is read from the DSPIx_POPR When the TX FIFO is disabled the TFFF TFUF and TXCTR fields in DSPIx_SR behave as if there...

Page 861: ...Every time an entry is transferred from the TX FIFO to the shift register the TX FIFO counter is decremented by one At the end of a transfer the TCF bit in the DSPIx_SR is set to indicate the completi...

Page 862: ...2 7 DSPI POP RX FIFO Register DSPIx_POPR for more information on DSPIx_POPR When the RX FIFO is not empty the RX FIFO drain flag RFDF in the DSPIx_SR is set The RFDF bit is cleared when the RX_FIFO i...

Page 863: ...from the selected source of the serialized data the slave DSPI asserts the MTRIG signal If the slave s internal hardware trigger signal is asserted and the TRRE is set the slave DSPI asserts MTRIG Th...

Page 864: ...tion 19 3 2 14 DSPI DSI Deserialization Data Register DSPIx_DDR Figure 19 20 DSI Deserialization Diagram 19 4 4 5 DSI Transfer Initiation Control Data transfers for a master DSPI in DSI configuration...

Page 865: ...very time a change in data is detected 19 4 4 5 3 Triggered Control For triggered control initiation of a transfer is controlled by the internal hardware trigger signal ht The TPOL bit in the DSPIx_DS...

Page 866: ...1 on IMUX for external IRQ 4 eTPUA output channel 18 5 5 Input 1 on IMUX for external IRQ 5 eTPUA output channel 17 6 6 Input 1 on IMUX for external IRQ 6 eTPUA output channel 16 7 7 Input 1 on IMUX f...

Page 867: ...nput 2 on IMUX for external IRQ 0 eTPUA output channel 14 2 2 Input 2 on IMUX for external IRQ 1 eTPUA output channel 15 3 3 Input 2 on IMUX for external IRQ 2 eTPUA output channel 0 4 4 Input 2 on IM...

Page 868: ...output channel 20 1 1 Input 3 on IMUX for external IRQ 15 eTPUA output channel 19 2 2 no connect eTPUA output channel 18 3 3 no connect eTPUA output channel 17 4 4 Input 3 on IMUX for external IRQ 2...

Page 869: ...tes a trigger signal on the MTRIG output The SIU_DISR must be configured to use serial or parallel chaining 19 4 4 7 1 Internal Muxing SIU Support for Serial and Parallel Chaining To support MTO each...

Page 870: ...ource for the SCKx input of a DSPI can be a pin or the SCKx output of any of the other DSPIs The source for the hardware trigger ht input can be the MTRIG signal from any of the other DSPIs The DSPI i...

Page 871: ...d SCKx signals DSPI B controls and initiates all transfers but the DSPI slaves each have a trigger output signal MTRIG that indicates to DSPI B that a trigger condition has occurred in the DSPI slaves...

Page 872: ...erialized it can assert the MTRIG signal to the DSPI master which initiates the transfer When a DSPI slave has its ht signal asserted its MTRIG signal asserts and propagates trigger signals from other...

Page 873: ...Transfer Initiation Control When there are SPI commands in the TX FIFO the SPI data has priority over the DSI frames When the TX FIFO is empty DSI transfer resumes Two peripheral chip select signals i...

Page 874: ...rame is stored in the DSPIx_COMPR The transfer priority logic selects the source of the serialized data and asserts the chip select signal Refer to Section 19 3 2 11 DSPI DSI Serialization Data Regist...

Page 875: ...ncy of the serial communication clock SCKx The system clock is divided by a baud rate prescaler defined by DSPIx_CTAR PBR and baud rate scaler defined by DSPIx_CTAR BR to produce SCKx with the possibi...

Page 876: ...ds in the DSPIx_CTARn registers select the after SCK delay The relationship between these variables is given in the following formula Table 19 24 shows an example of the computed after SCK delay 19 4...

Page 877: ...relative to PCS signals Figure 19 31 Peripheral Chip Select Strobe Timing The delay between the assertion of the PCSx signals and the assertion of PCSS is selected by the PCSSCK field in the DSPIx_CTA...

Page 878: ...d number of bits to transfer must be identical for the master device and the slave device to ensure proper transmission The DSPI supports four different transfer formats Classic SPI with CPHA 0 Classi...

Page 879: ...serial data output signals For the rest of the frame the master and the slave sample their SINx pins on the odd numbered clock edges and changes the data on their SOUTx pins on the even numbered clock...

Page 880: ...aster and slave sample their SINx pins For the rest of the frame the master and the slave change the data on their SOUTx pins on the odd numbered clock edges and sample their SINx pins on the even num...

Page 881: ...the PCSx signal After the PCSx to SCKx delay has elapsed the first SCKx edge is generated The slave samples the master SOUTx signal on every odd numbered SCKx edge The slave also places new data on t...

Page 882: ...UT pins at the first edge of SCK The slave samples the master SOUT signal on the even numbered edges of SCK The master samples the slave SOUT signal on the odd numbered SCK edges starting with the 3rd...

Page 883: ...ovides the flexibility to handle both cases The continuous selection format is enabled for the SPI configuration by setting the CONT bit in the SPI command Continuous selection is enabled for the DSI...

Page 884: ...7 the period length at the start of the next transfer is the sum of tASC and tCSC i e it does not include a half clock period The default settings for these provide a total of four system clocks In ma...

Page 885: ...in the DSPIx_MCR Continuous SCK is valid in all configurations Continuous SCK is only supported for CPHA 1 Setting CPHA 0 is ignored if the CONT_SCKE bit is set Continuous SCK is supported for modifie...

Page 886: ...lay The delay after transfer is fixed at one SCK cycle Figure 19 39 shows timing diagram for continuous SCK format with continuous selection disabled Figure 19 39 Continuous SCK Timing Diagram CONT 0...

Page 887: ...igure 19 32 and Figure 19 33 that illustrate when EOQF is set 19 4 9 2 Transmit FIFO Fill Interrupt or DMA Request TFFF The transmit FIFO fill request indicates that the TX FIFO is not full The transm...

Page 888: ...the state of the ROOE bit in the DSPIx_MCR the data from the transfer that generated the overflow is either ignored or shifted in to the shift register If the ROOE bit is set the incoming data is shi...

Page 889: ...ampled the EOQ flag EOQF in the DSPIx_SR is set 3 The setting of the EOQF flag disables both serial transmission and serial reception of data putting the DSPI in the STOPPED state The TXRXS bit is neg...

Page 890: ...ate Scaler Values DSPI_CTAR BR 2 25 0 MHz 16 7 MHz 10 0 MHz 7 14 MHz 4 12 5 MHz 8 33 MHz 5 00 MHz 3 57 MHz 6 8 33 MHz 5 56 MHz 3 33 MHz 2 38 MHz 8 6 25 MHz 4 17 MHz 2 50 MHz 1 79 MHz 16 3 12 MHz 2 08...

Page 891: ...Rs to match the default cases for the possible combinations of the MPC5xx family control bits in its command RAM The defaults for the MPC5xx family are based on a system clock of 40 MHz Table 19 31 De...

Page 892: ...a memory mapped counter for each FIFO The pointer to the first in entry in each FIFO is memory mapped For the TX FIFO the first in pointer is the transmit next pointer TXNXTPTR For the RX FIFO the fi...

Page 893: ...O base base address of transmit FIFO TXCTR transmit FIFO counter TXNXTPTR transmit next pointer TX FIFO depth transmit FIFO depth implementation specific 19 5 5 2 Address Calculation for the First in...

Page 894: ...categories module specific modes such as master slave and module disable modes and an MCU specific mode debug mode To These modes can be divided into two categories module specific modes such as mast...

Page 895: ...Deserial Serial Peripheral Interface DSPI MPC5565 Microcontroller Reference Manual Rev 1 0 19 72 Freescale Semiconductor...

Page 896: ...eSCI Block Diagram IRQ generation Receive wake up control Receive shift register eSCI data register LIN receive register LIN transmit register DMA interface TX DMA RX DMA RDRF OR IRQ ORING IRQ to CPU...

Page 897: ...CI registers via the slave bus When the eSCI module is not used in the application set the MDIS bit 20 1 3 Features The eSCI includes these features Full duplex operation Standard mark space non retur...

Page 898: ...2 eSCI Receive Pin RXDA RXDB These signals receive data input for the eSCI 20 3 Memory Map and Register Definition 20 3 1 Overview This section provides a detailed description of all memory and regis...

Page 899: ...rol register 1 32 Base 0x0004 ESCIx_CR2 eSCI control register 2 16 Base 0x0006 ESCIx_DR eSCI data register 16 Base 0x0008 ESCIx_SR eSCI status register 32 Base 0x000C ESCIx_LCR LIN control register 32...

Page 900: ...start bit 8 data bits 1 stop bit 1 1 start bit 9 data bits 1 stop bit 20 WAKE Wake up condition Determines which condition wakes up the eSCI a logic 1 address mark in the most significant bit MSB posi...

Page 901: ...OR to generate interrupt requests The interrupt is suppressed in RX DMA mode 0 RDRF and OR interrupt requests disabled 1 RDRF and OR interrupt requests enabled 27 ILIE Idle line interrupt enable Enabl...

Page 902: ...0 0 0 0 Figure 20 3 eSCI Control Register 2 ESCIx_CR2 Table 20 4 ESCIx_CR2 Field Description Field Description 0 MDIS Module disable By default the module is enabled but can be disabled by writing a 1...

Page 903: ...when a bit error is asserted This allows to stop driving the LIN bus quickly after a bit error has been detected 0 Byte is completely transmitted 1 Byte is partially transmitted 10 11 Reserved 12 ORIE...

Page 904: ...8 R8 is the ninth data bit received when the eSCI is configured for 9 bit data format M 1 1 T8 Transmit bit 8 T8 is the ninth data bit transmitted when the eSCI is configured for 9 bit data format M...

Page 905: ...ata register since last time software cleared RDRF 1 Received data available in eSCI data register 3 IDLE Idle line flag IDLE is set when 10 consecutive logic 1s if M 0 or 11 consecutive logic 1s if M...

Page 906: ...s set when the ESCIx_LTR register becomes free Clear TXRDY by writing it with 1 18 LWAKE Received LIN wake up signal A LIN slave has sent a wake up signal on the bus When this signal is detected the L...

Page 907: ...a wake up signal on the LIN bus This must be set before a transmission if the bus is in sleep mode This bit auto clears so a read from this bit always returns 0 According to LIN 2 0 generating a valid...

Page 908: ...XREG ready interrupt enable Generates an Interrupt when new data can be written to the LIN TXREG For a list of interrupt enables and flags Refer to Table 20 21 10 WUIE RX wake up interrupt enable Gene...

Page 909: ...L0 T8 T0 D0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 20 7 LIN Transmit Re...

Page 910: ...CRC pattern as required LIN 1 x slaves only accepts frames with 2 4 or 8 data bytes 8 31 Reserved Table 20 10 ESCIx_LTR Third Byte Field Descriptions Field Description 0 HDCHK Header checksum enable I...

Page 911: ...er 8 31 Reserved Table 20 11 ESCIx_LTR Rx Frame Fourth Byte Field Description Field Description 0 7 Tn Timeout bit n Sets the counter to determine a NO_RESPONSE_ERROR if the frame is a read access to...

Page 912: ...9 LIN Receive Register ESCIx_LRR Table 20 13 ESCIx_LRR Field Descriptions Field Description 0 7 Dn Data bit n Provides received data bytes from RX frames Data is only valid when the ESCIx_SR RXRDY fl...

Page 913: ...vices including other CPUs The eSCI transmitter and receiver operate independently although they use the same baud rate generator The CPU monitors the status of the eSCI writes the data to be transmit...

Page 914: ...n and can be used repeatedly without rewriting it A frame with nine data bits has a total of 11 bits The two different data formats are illustrated in Figure 20 12 Table 20 15 and Table 20 16 show the...

Page 915: ...t target frequency Table 20 17 lists some examples of achieving target baud rates with a system clock frequency of 128 MHz Table 20 15 Example of 8 bit Data Formats Start Bit Data Bits Address Bits Pa...

Page 916: ...D05 38 404 2 400 2 2400 01 0x1A0A 19 202 1 200 1 1200 01 Table 20 17 Baud Rates Example System Clock 128 MHz continued Bits SBR 0 12 Receiver Clock Hz Transmitter Clock Hz TargetBaud Rate Error M TXD...

Page 917: ...smitter buffer ESCIx_DR while the shift register is still shifting out the first byte To initiate an eSCI transmission 1 Configure the eSCI a Turn on the module by clearing ESCIx_CR2 MDIS if this bit...

Page 918: ...is not transmitting a frame the TXD output goes to the idle condition logic 1 If at any time software clears the TE bit in eSCI control register 1 ESCIx_CR1 the transmit enable signal goes low and the...

Page 919: ...4 4 Idle Characters An idle character contains all logic 1s and has no start stop or parity bit Idle character length depends on the M bit in eSCI control register 1 ESCIx_CR1 The preamble is a synch...

Page 920: ...ected the following actions are performed The LIN frame is aborted provided LDBG 0 The bit error flag BERR is set If SBSTP is 0 the remainder of the byte is transmitted normally If SBSTP is 1 the rema...

Page 921: ...CI data register is the buffer read only during receive between the internal data bus and the receive shift register After a complete frame shifts into the receive shift register the data portion of t...

Page 922: ...c performs an asynchronous search for a logic 0 preceded by three logic 1s When the falling edge of a possible start bit occurs the RT clock begins to count to 16 Figure 20 17 Receiver Data Sampling T...

Page 923: ...of the RT8 RT9 and RT10 start bit samples are logic 1s following a successful start bit verification the noise flag NF is set To verify a stop bit and to detect noise recovery logic takes samples at...

Page 924: ...DRF flag is set 20 4 5 5 Baud Rate Tolerance When a transmitting device operates at a baud rate below or above the receiver baud rate accumulated bit time misalignment can cause one of the three stop...

Page 925: ...s x 16 RT cycles 147 RT cycles The maximum percent difference between the receiver count and the transmitter count of a slow 8 bit data character with no errors is 4 63 as is shown below For a 9 bit d...

Page 926: ...as is shown below For a 9 bit data character data sampling of the stop bit takes the receiver 170 RT cycles as shown below With the misaligned character shown in Figure 20 20 the receiver counts 170 R...

Page 927: ...mains on standby until another idle character appears on the RXD signal Idle line wake up requires that messages be separated by at least one idle character and that no message contains idle character...

Page 928: ...XD pin should be set for open drain operation SIU_PCRnn ODE 1 Optionally if the external transmitting device is also open drain a weak pullup can be enabled Refer to Section 6 3 1 12 Pad Configuration...

Page 929: ...with details and descriptions in Table 20 21 Table 20 21 eSCI Interrupt Flags Sources Mask Bits and Descriptions Interrupt Source Flag Description Source Local Enable Transmitter TDRE Indicates that...

Page 930: ...IE Receiver NF Detect noise error on receiver input The NF interrupt is set when the eSCI detects noise on the receiver input ESCIx_SR 5 NFIE Receiver FE Framing error has occurred The interrupt is se...

Page 931: ...CIE LIN CKERR Checksum error detected If an RX frame has the checksum checking flag set and the last byte does not match the calculated checksum the checksum error CKERR flag is set Clear the CKERR f...

Page 932: ...according to the LIN specification The eSCI must be configured for 2 wire operation 2 wires connected to the LIN transceiver with 8 data bytes and no parity Normally a 13 bit break is used but the eS...

Page 933: ...tes to the ESCIx_LTR specify the LIN frame data After the LIN frame data is specified the eSCI LIN hardware starts to generate a LIN frame First the eSCI transmits a break field The sync field is tran...

Page 934: ..._SR RXRDY bit must be checked either with an interrupt RX DMA interface or by polling to detect incoming data bytes The checksum byte normally does not appear in the ESCIx_LRR instead the LIN hardware...

Page 935: ...aster is regularly creating some bus activity Otherwise the timeout state needs to be detected by the application software for example by setting a timer Both LIN masters and LIN slaves can cause the...

Page 936: ...o reset the LIN FSM immediately stop bus transfers and suspend DMA requests until the BERR flag is cleared Use the following bit settings to perform these functions ESCIx_LCR LDBG 0 ESCIx_CR2 SBSTP 1...

Page 937: ...Enhanced Serial Communication Interface eSCI MPC5565 Microcontroller Reference Manual Rev 1 0 20 42 Freescale Semiconductor...

Page 938: ...xCAN2 module contains a 1024 byte embedded memory capable of storing up to 64 message buffers MBs The respective functions are described in subsequent sections Each FlexCAN module contains two embedde...

Page 939: ...ting the specific requirements of this field real time processing reliable operation in the EMI environment of a vehicle cost effectiveness and required bandwidth The FlexCAN2 module is a full impleme...

Page 940: ...ID Programmable for either global compatible with previous versions or individual receive ID masking Maskable self reception by setting MCR SRXDIS Full implementation of the CAN protocol specificatio...

Page 941: ...edgments 21 1 4 4 Loop Back Mode The module enters this mode when the LPB bit in the CANx_CR is asserted In this mode FlexCAN performs an internal loop back that can be used for self test operation Th...

Page 942: ...at the module base address extra space for MB storage and 1024 bytes for 64 MBs 21 3 1 Memory Map The complete memory map for a FlexCAN2 module with its 64 MBs is shown in Table 21 2 Except for the b...

Page 943: ...presented Base 0x001C CANx_ECR Error counter register 32 Base 0x0020 CANx_ESR Error and status register 32 Base 0x0024 CANx_IMRH Interrupt masks high register 32 Base 0x0028 CANx_IMRL Interrupt masks...

Page 944: ...lexCAN2 transmits this bit as 1 recessive and receives it as 0 dominant it is interpreted as arbitration loss If this bit is transmitted as 0 dominant then if it is received as 1 recessive the FlexCAN...

Page 945: ...N A frame was overwritten into a full buffer 0010 If the code indicates OVERRUN but the CPU reads the C S word and then unlocks the MB when a new frame is written to the MB the code returns to FULL 01...

Page 946: ...emote request frame with the ID of the MB If a match occurs this MB is allowed to participate in the current arbitration process and the CODE field is automatically updated to 1110 to allow the MB to...

Page 947: ...2 is disabled Refer to Section 21 4 6 1 Freeze Mode for more information 0 No freeze mode request 1 Enters freeze mode if the FRZ bit is asserted 4 NOTRDY FlexCAN2 not ready Indicates that FlexCAN2 is...

Page 948: ...defines whether FlexCAN is allowed to receive frames transmitted by itself If this bit is asserted frames transmitted by the module will not be stored in any MB regardless if the MB is programmed wit...

Page 949: ...write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R PRESDIV RJW PSEG1 PSEG2 W Reset1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R BOFF MSK ERR MSK CLK_ SRC LPB TWRN MSK...

Page 950: ...n loop back mode Refer to Section 21 1 4 Modes of Operation for information about this operating mode 0 Loop back disabled 1 Loop back enabled 20 TWRNMSK This bit provides a mask for the TX Warning In...

Page 951: ...ining the bus After negation the BOFFREC bit can be re asserted again during bus off but it will only be effective the next time the module enters bus off If BOFFREC was negated when the module entere...

Page 952: ...in normal operation Locked frames which had matched a MB through a mask may be transferred into the MB upon release but may no longer match Table 21 9 shows some examples of ID masking for standard an...

Page 953: ...r MB14 uses RX14MASK Address Base 0x0010 CANx_RXGMASK Base 0x0014 CANx_RX14MASK Base 0x0018 CANx_RX15MASK Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 MI28 MI27 MI26 MI25 MI24...

Page 954: ...s One mask register is provided for each message buffer for individual ID masking per message buffer The meaning of each mask bit is the following Mask bit 0 The corresponding incoming ID bit is a don...

Page 955: ...XECTR decrements to a value less than or equal to 127 while the other already satisfies this condition the FLTCONF field in the CANx_ESR is updated to reflect the error active state If the value of TX...

Page 956: ...ch are interrupt flags that can be cleared by writing 1 to them writing 0 has no effect Refer to Section 21 4 7 Interrupts for more details NOTE A read clears BIT1ERR BIT0ERR ACKERR CRCERR FRMERR and...

Page 957: ...ERR Bit 0 error Indicates when an inconsistency occurs between the transmitted and the received message in a bit A read clears BIT0ERR 0 No such occurrence 1 At least one bit sent as dominant is recei...

Page 958: ...t the FLTCONF field will not be affected by soft reset if the LOM bit is asserted 00 Error active 01 Error passive 1X Bus off 28 Reserved 29 BOFFINT Bus off interrupt This status bit is set when FlexC...

Page 959: ...xCAN2 message buffer MB63 to MB32 Interrupt 0 The corresponding buffer Interrupt is disabled 1 The corresponding buffer Interrupt is enabled Note Setting or clearing a bit in the IMRH register can ass...

Page 960: ...35I BUF 34I BUF 33I BUF 32I W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21 12 Interrupt Flags High Register CANx_IFRH Table 21 15 CAN...

Page 961: ...ds of the control and status word to activate the TX MB The first and last steps are mandatory 21 4 2 1 Arbitration Process This process selects which will be the next MB to be transmitted All MBs pro...

Page 962: ...MB is updated a status flag is set in CANx_IFRL or CANx_IFRH and an MB interrupt is generated if allowed by the corresponding interrupt mask register bit 21 4 3 Receive Process The CPU prepares a mes...

Page 963: ...an change if the match was due to mask 21 4 3 2 Reception Queue A queue of received messages can be implemented that allows the CPU more time for servicing MBs By programming more than one MB with the...

Page 964: ...ocesses during the current match arbitration round Any CPU write access to a control and status word of the MB structure deactivates that MB excluding it from the current RX TX process However deactiv...

Page 965: ...If the CPU reads a RX MB while it is being transferred into from SMB then the BUSY bit is set in the CODE field of the control and status word To assure data coherency the CPU should wait until this...

Page 966: ...frame is independent of the DLC field in the remote frame that initiated its transmission 21 4 5 2 Overload Frames FlexCAN2 will transmit overload frames due to detection of following conditions on CA...

Page 967: ...It can be programmed by setting the PROPSEG and the PSEG1 fields of the CTRL register so that their sum plus 2 is in the range of 4 to 16 time quanta Time segment 2 This segment represents the phase...

Page 968: ...tions must be observed A valid CAN bit timing must be programmed as indicated in Figure 21 15 The system clock frequency cannot be smaller than the oscillator clock frequency i e the PLL cannot be pro...

Page 969: ...es Sets the NOTRDY and FRZACK bits in CANx_MCR After requesting freeze mode the user must wait for the FRZACK bit to be asserted in CANx_MCR before executing any other action otherwise FlexCAN2 can op...

Page 970: ...a particular buffer under the assumption that the buffer is initialized for either transmission or reception Each of the buffers has assigned a flag bit in the CANx_IFRH or CANx_IFRL registers The bit...

Page 971: ...TX pin is in recessive state and FlexCAN2 does not initiate frame transmission nor receives any frames from the CAN bus Note that the message buffer contents are not affected by reset so they are not...

Page 972: ...h occurs a newly received frame is transferred moved in to the first that is lowest entry matching MB Only MBs marked as EMPTY FULL or OVERRUN will participate in the internal matching process at the...

Page 973: ...Preface MPC5565 Microcontroller Reference Manual Rev 1 0 21 36 Freescale Semiconductor...

Page 974: ...also contains POR circuits for the 1 5 V supply VDDSYN and the VDDE supply that powers the RESET pad 22 1 1 Block Diagram The block diagram of the VRC and POR module is shown in Figure 22 1 The diagra...

Page 975: ...ator controller slowly turns on the pass transistor while the 3 3 V POR is asserted The pass transistor is completely turned on by the time the 3 3 V POR negates Table 22 1 Voltage Regulator Controlle...

Page 976: ...being monitored drops below the specified threshold The entire device is in power on reset if any of these supplies are below the values specified in the MPC5565 Microcontroller Data Sheet Power on r...

Page 977: ...he user must follow the specified power sequence 22 4 2 2 3 3 V POR Circuit The 3 3 V POR circuit is used to ensure that VDDSYN is high enough that the FMPLL begins to operate correctly 22 4 2 3 RESET...

Page 978: ...ng characteristics 22 5 3 Power Sequencing Requirements This section describes the following power sequencing requirements for the device If an external 1 5 V power supply is used and VRC33 is tied to...

Page 979: ...VRC33 Grounded The 1 5 V VDD supply must rise to 1 35 V before the 3 3 V VDDSYN and the RESET supplies rise above 2 0 V This ensures that digital logic in the PLL for the 1 5 V supply does not begin t...

Page 980: ...n Refer to the following sections or documents for more information Section 22 5 3 4 Pin Values after POR Negates MPC5565 Microcontroller Data Sheet for the VDD33_LAG specification 22 5 3 4 Pin Values...

Page 981: ...SemiconductorTM NJD2873 and Phillips SemiconductorTM BCP68 In Section 22 4 2 POR Circuits in the first sentence FROM individual POR circuits will negate whenever TO individual POR circuits will asser...

Page 982: ...ode select TMS and test clock input TCK TDI TDO TMS and TCK are compliant with the IEEE 1149 1 2001 standard and are shared with the NDI through the test access port TAP interface 23 1 1 Block Diagram...

Page 983: ...egister a boundary scan register and a device identification register The size of the boundary scan register is 464 bits A TAP controller state machine that controls the operation of the data register...

Page 984: ...ss Mode When no test operation is required the BYPASS instruction can be loaded to place the JTAGC into bypass mode While in bypass mode the single bit bypass shift register is used to provide a minim...

Page 985: ...the TAP controller is in the Shift IR state and latched on the falling edge of TCK in the Update IR state The latched instruction value can only be changed in the update IR and test logic reset TAP c...

Page 986: ...O when the EXTEST SAMPLE or SAMPLE PRELOAD instructions are active It is used to capture input pin data force fixed values on output pins and select a logic value and direction for bidirectional pins...

Page 987: ...nstruction For more detail on TAP sharing via JTAGC instructions refer to Section 23 4 4 2 ACCESS_AUX_TAP_x Instructions Data is shifted between TDI and TDO though the selected register starting with...

Page 988: ...Machine Test logic reset Run test idle Select DR scan Select IR scan Capture DR Capture IR Shift DR Shift IR Exit1 DR Exit1 IR Pause DR Pause IR Exit2 DR Exit2 IR Update DR Update IR 1 0 1 1 1 0 0 0 0...

Page 989: ...uctions This section gives an overview of each instruction refer to the IEEE 1149 1 2001 standard for more details The JTAGC implements the IEEE 1149 1 2001 defined instructions listed in Table 23 3 T...

Page 990: ...ruction CLAMP allows the state of signals driven from MCU pins to be determined from the boundary scan register while the bypass register is selected as the serial path between TDI and TDO CLAMP enhan...

Page 991: ...he instruction samples the system data and control signals on the MCU input pins and just before the boundary scan register cells at the output pins This sampling occurs on the rising edge of TCK in t...

Page 992: ...t synchronized to TCK internally Any mixed operation using both the test logic and the system functional logic requires external synchronization To initialize the JTAGC module and enable access to reg...

Page 993: ...IEEE 1149 1 Test Access Port Controller JTAGC MPC5565 Microcontroller Reference Manual Rev 1 0 23 12 Freescale Semiconductor...

Page 994: ...z6 core interface NZ6C3 In this chapter the NZ6C3 interface is discussed in Section 24 10 e200z6 Class 3 Nexus Module NZ6C3 through Section 24 11 NZ6C3 Memory Map Register Definition Nexus crossbar eD...

Page 995: ...halt step continue Data watchpoint trace Buffer Program data ownership watchpoint trace R W register R W data halt step continue Read write access Buffer NZ6C3 Nexus port controller NPC JTAG port cont...

Page 996: ...hip trace via ownership trace messaging OTM OTM facilitates ownership trace by providing visibility of which process ID or operating system task is activated An ownership trace message is transmitted...

Page 997: ...ts Nexus based breakpoint watchpoint configuration and single step support Run time access to the on chip memory map via the Nexus read write access protocol This feature supports accesses for run tim...

Page 998: ...In reduced port mode a subset of the available MDO pins are used to transmit messages All trace features are enabled or can be enabled by writing the configuration registers via the JTAG port The numb...

Page 999: ...VTO signals from all Nexus modules that implement the signal 24 2 1 2 Event In EVTI EVTI is used to initiate program and data trace synchronization messages or to generate a breakpoint EVTI is edge se...

Page 1000: ...1 5 Ready RDY RDY is an output pin that indicates when a device is ready for the next access 24 2 1 6 JTAG Compliancy JCOMP The JCOMP signal enables or disables the TAP controller The TAP controller i...

Page 1001: ...atus NZ6C3_DS 0b0000 6 e200z6 User Base Address NZ6C3_UBA 0b0000 7 Read Write Access Control Status NZ6C3_RWCS 0b0000 9 Read Write Access Address NZ6C3_RWA 0b0000 10 Read Write Access Data NZ6C3_RWD 0...

Page 1002: ...akpoint Watchpoint Control 1 NSEDI_eTPU1_BWC1 0b0010 23 eTPU1 Breakpoint Watchpoint Control 2 NSEDI_eTPU1_BWC2 0b0010 24 eTPU1 Breakpoint Watchpoint Control 3 NSEDI_eTPU1_BWC3 0b0010 30 eTPU1 Breakpoi...

Page 1003: ...Compare 2 IAC2 010 0010 Instruction Address Compare 3 IAC3 010 0011 Instruction Address Compare 4 IAC4 010 0100 Data Address Compare 1 DAC1 010 0101 Data Address Compare 2 DAC2 010 0110 010 1011 Reser...

Page 1004: ...ing MCKO_EN in the PCR places the NDI in enabled mode and enables MCKO The frequency of MCKO is selected by writing the MCKO_DIV field Asserting or negating the FPM bit selects full port or reduced po...

Page 1005: ...d if a reserved encoding is programmed is SYS_CLK 2 24 4 4 Nexus Messaging Most of the messages transmitted by the NDI include a SRC field This field is used to identify which source generated the mes...

Page 1006: ...re the same as the JTAGC device identification register 24 5 1 Overview The device incorporates multiple modules that require development support Each of these modules implements a development interfa...

Page 1007: ...try into the Capture DR state the single bit shift register is set to a logic 0 Therefore the first bit shifted out after selecting the bypass register is always a logic 0 24 6 2 2 Instruction Registe...

Page 1008: ...Identification Number W Reset 0 0 0 0 1 0 0 0 0 0 0 1 0 1 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Part Identification Number continued Manufacturer Identity Code 1 W Reset 0 1 0 1 0 0 0 0 0 0 0 1...

Page 1009: ...nfiguration Register PCR Table 24 11 PCR Field Descriptions Field Description 31 FPM Full port mode Determines if the auxiliary output port uses the full MDO port or a reduced MDO port to transmit mes...

Page 1010: ...tive to the system clock frequency when MCKO_EN is asserted The table below shows the meaning of MCKO_DIV values In this table SYS_CLK represents the system clock frequency 25 1 Reserved 0 PSTAT_EN Pr...

Page 1011: ...iliary port is found in Section 24 2 External Signal Description 24 7 2 1 Output Message Protocol The protocol for transmitting messages via the auxiliary port is accomplished with the MSEO functions...

Page 1012: ...MDO pins The device ID message can also be sent out serially through TDO Table 24 13 describes the device ID message that the NPC can transmit on the auxiliary port The TCODE is the first packet tran...

Page 1013: ...port boundary it is necessary to extend and zero fill the remaining bits after the highest order bit so that it can end on a port boundary Multiple fixed length packets may start and or end on a sing...

Page 1014: ...Table 24 14 The value of the NEXUS ENABLE instruction is 0b0000 Each unimplemented instruction acts like the BYPASS instruction The size of the NPC instruction register is 4 bits Data is shifted betwe...

Page 1015: ...T RUN TEST IDLE SELECT DR SCAN SELECT IR SCAN CAPTURE DR CAPTURE IR SHIFT DR SHIFT IR EXIT1 DR EXIT1 IR PAUSE DR PAUSE IR EXIT2 DR EXIT2 IR UPDATE DR UPDATE IR 1 0 1 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0...

Page 1016: ...in the UPDATE IR state At this point the Nexus controller state machine shown in Figure 24 10 transitions to the REG_SELECT state The Nexus controller has three states idle register select and data a...

Page 1017: ...r the value is loaded from the IEEE 1149 1 2001 shifter to the register during the UPDATE DR state When reading a register there is no requirement to shift out the entire register contents Shifting ma...

Page 1018: ...O MCKO is an output clock to the development tools used for the timing of MSEO and MDO pin functions MCKO is derived from the system clock and its frequency is determined by the value of the MCKO_DIV...

Page 1019: ...sters To initialize the TAP for NPC register accesses the following sequence is required 1 Enable the NPC TAP controller This is achieved by asserting JCOMP and loading the ACCESS_AUX_TAP_NPC instruct...

Page 1020: ...functions transfer protocols and standard development features of the NZ6C3 module The development features supported are Program trace data trace watchpoint messaging ownership trace and read write a...

Page 1021: ...the NPC is omitted and the behavior described as if the module has its own dedicated auxiliary port The auxiliary port is fully described in Section 24 2 External Signal Description 24 10 2 Block Diag...

Page 1022: ...how data flows through the embedded system This may include DRM and or DWM JTAG Compliant Device complying to IEEE 1149 1 JTAG standard JTAG IR DR Sequence JTAG instruction register IR scan to load a...

Page 1023: ...rigger enable of program and or data trace messaging Higher speed data input output via the auxiliary port Auxiliary interface for higher data input output Configurable minimum and maximum message dat...

Page 1024: ...atus 6 6 TCODE Fixed TCODE number 0 0x00 4 4 SRC Fixed Source processor identifier 8 8 STATUS Fixed Debug status register DS 31 24 Ownership Trace Message 6 6 TCODE Fixed TCODE number 2 0x02 4 4 SRC F...

Page 1025: ...h Message w Sync1 6 6 TCODE Fixed TCODE number 12 0x0C 4 4 SRC Fixed Source processor identifier 1 8 I CNT Variable Number of sequential instructions executed since last taken branch 1 32 F ADDR Varia...

Page 1026: ...4 4 SRC Fixed Source processor identifier 1 8 I CNT Variable Number of sequential instructions executed since last taken branch 1 32 U ADDR Variable Unique part of target address for taken branches e...

Page 1027: ...ram trace The advantages for each are discussed in Section 24 11 12 1 Branch Trace Messaging BTM If the branch history method is selected the shaded TCODES above will not be messaged out Table 24 20 E...

Page 1028: ...ory bit Branch History This type of packet is terminated by a stop bit set to a 1 after the last history bit Table 24 22 Event Code Encoding TCODE 33 Event Code Description 0000 Entry into Debug Mode...

Page 1029: ...0 as the least significant bit This bit ordering is consistent with the ordering defined by the IEEE ISTO 5001 standard Table 24 24 details the register map for the NZ6C3 module Table 24 24 NZ6C3 Memo...

Page 1030: ...controller NPC not in the NZ6C3 module The device s CSC register is readable through Nexus3 but the PCR is shown for reference only OPC 0 MCK_EN MCK_DIV 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 1031: ...1 OPC1 Output port mode control 0 Reduced port mode configuration four MDO pins 1 Full port mode configuration 12 MDO pins 30 29 MCK_DIV 1 0 1 MCKO clock divide ratio refer to note below 00 MCKO is 1x...

Page 1032: ...CR but have no effect Nexus Reg 0x0003 Access R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R EWC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0...

Page 1033: ...27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DBG 0 0 0 LPC CHK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1034: ...DV W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24 18 Read Write Access Control Status Register RWCS Table 24 29 RWCS Field Description Field Description 31 AC Access control 0 End access 1 Start a...

Page 1035: ...ion Write Action ERR DV Read access has not completed Write access completed without error 0 0 Read access error has occurred Write access error has occurred 1 0 Read access completed without error Wr...

Page 1036: ...0 Program trace start control 000 Trigger disabled 001 Use watchpoint 0 IAC1 from Nexus1 010 Use watchpoint 1 IAC2 from Nexus1 011 Use watchpoint 2 IAC3 from Nexus1 100 Use watchpoint 3 IAC4 from Nexu...

Page 1037: ...1 Use watchpoint 0 IAC1 from Nexus1 010 Use watchpoint 1 IAC2 from Nexus1 011 Use watchpoint 2 IAC3 from Nexus1 100 Use watchpoint 3 IAC4 from Nexus1 101 Use watchpoint 4 DAC1 from Nexus1 110 Use watc...

Page 1038: ...ce on instruction accesses 2 DI2 Data access instruction access trace 2 0 Condition trace on data accesses 1 Condition trace on instruction accesses 1 0 Reserved Nexus Reg 0x000E Access R W 31 30 29 2...

Page 1039: ...le 24 5 For the NZ6C3 module the OCMD value is 0b00_0111_1100 After the ACCESS_AUX_TAP_ONCE instruction has been loaded the JTAG OnCE port allows tool target communications with all Nexus3 registers a...

Page 1040: ...evel or object oriented language It offers the highest level of abstraction for tracking operating system software execution This is especially useful when the developer is not interested in debugging...

Page 1041: ...eue while it is being emptied the error message will incorporate the OTM only error encoding 00000 If both OTM and either BTM or DTM messages attempt to enter the queue the error message will incorpor...

Page 1042: ...virtual address bus between the CPU and MMU attribute signals and CPU status 24 11 12 1 Branch Trace Messaging BTM Traditional branch trace messaging facilitates program trace by providing the follow...

Page 1043: ...aken Certain instructions evsel generate a pair of predicate bits which are both reported as consecutive bits in the history field Branch history messages solve predicated instruction tracking and sav...

Page 1044: ...tatus messages and error messages are also supported 24 11 12 2 1 Indirect Branch Messages History Indirect branches include all taken branches whose destination is determined at run time interrupts a...

Page 1045: ...his message is generated the synchronization is delayed until the next branch trace message that is not a resource full message The current value of the history buffer is transmitted as part of the re...

Page 1046: ...full The FIFO will discard incoming messages until it has completely emptied the queue After it is emptied an error message will be queued The error encoding will indicate which types of messages atte...

Page 1047: ...ast with sync message occurred Upon direct indirect branch after assertion of the event in EVTI pin if the EIC bits within the DC1 register have enabled this feature Upon direct indirect branch after...

Page 1048: ...pes of messages attempted to be queued while the FIFO was being emptied The next BTM message in the queue will be a direct indirect branch with sync message Periodic Program Trace Sync A forced synchr...

Page 1049: ...ess with the previously decoded address gives the current address Previous address A1 0x0003FC01 New address A2 0x0003F365 Figure 24 38 Relative Address Generation and Re creation Collision Priority A...

Page 1050: ...n second conditions 24 11 12 3 4 Sequential Instruction Count I CNT The I CNT packet is present in all BTM messages For traditional branch messages I CNT represents the number of sequential instructio...

Page 1051: ...ng DRM as per the IEEE ISTO 5001 2003 standard TCODE 28 MCKO MSEO Source Processor 0b0000 Number of Sequential Instructions 0 Relative Address 0xA5 Branch History 0b1010_0101 with Stop MDO 1 0 11 01 0...

Page 1052: ...6 watchpoints are configured within the Nexus1 module 24 11 13 2 DTM Message Formats The Nexus3 module supports five types of DTM messages data write data read data write synchronization data read syn...

Page 1053: ...e will incorporate error encoding 01000 NOTE The OVC bits within the DC1 register can be set to delay the CPU to alleviate but not eliminate potential overrun situations Error information is messaged...

Page 1054: ...th sync message Queue Overrun An error message occurs when a new message cannot be queued due to the message queue being full The FIFO will discard messages until it has completely emptied the queue A...

Page 1055: ...s achieved via the address range defined by the DTEA and DTSA registers and by the RC1 2 field in the DTC All e200z6 initiated read write accesses which fall inside or outside these address ranges as...

Page 1056: ...ment tool should use this indication to invalidate the previous DTM 24 11 13 4 Data Trace Timing Diagrams Eight MDO Configuration Figure 24 47 Data Trace Data Write Message e200z6 bus cycle accesses m...

Page 1057: ...s is supported through the e200z6 Nexus1 module The e200z6 Nexus1 module is capable of setting multiple address and or data watchpoints Please refer to the e200z6 Core Reference Manual for more inform...

Page 1058: ...e watchpoint only error encoding 00110 If an OTM and or program trace and or data trace message also attempts to enter the queue while it is being emptied the error message will incorporate error enco...

Page 1059: ...other non cached memory can be accessed via the standard memory map settings All accesses are setup and initiated by the read write access control status register RWCS as well as the read write acces...

Page 1060: ...register index of 0xA refer to Table 24 24 Configure as follows Write Data 0xnnnnnnnn write data 4 The NZ6C3 module will then arbitrate for the system bus and transfer the data value from the data buf...

Page 1061: ...address register RWA For each access within the burst the address from the RWA register is incremented to the next doubleword size specified in the SZ field modulo the length of the burst and the num...

Page 1062: ...register When the transfer has completed without error ERR 0b0 the address from the RWA register is incremented to the next word size specified in the SZ field and the number from the CNT field is dec...

Page 1063: ...ite accesses to the e200z6 system bus will return a transfer error If this occurs 1 The access is terminated without re trying AC bit is cleared 2 The ERR bit in the RWCS register is set 3 The error m...

Page 1064: ...processor fixed Ix Number of instructions variable Ax Unique portion of the address variable Table 24 41 illustrates an example of direct branch message with 12 MDO 2 MSEO Note that T0 and I0 are the...

Page 1065: ...or end of last message 1 I1 I0 S3 S2 S1 S0 T5 T4 T3 T2 T1 T0 0 0 Start Message 2 0 0 0 0 0 0 0 0 0 0 I3 I2 1 1 End Packet End Message 3 X X X X S1 S0 T5 T4 T3 T2 T1 T0 0 0 Start of Next Message Table...

Page 1066: ...Command write to read write access address register RWA 2 37 Write RWA initialize starting read address data input on TDI 3 13 Nexus Command write to read write control status register RWCS 4 37 Writ...

Page 1067: ...rences are made to the auxiliary port and its specific signals such as MCKO MSEO 1 0 MDO 12 0 and others In actual use the device NPC module arbitrates the access of the single auxiliary port To simpl...

Page 1068: ...c 24 13 External Signal Description The NXDM module uses the same pins and pin protocol as defined in Section 24 2 External Signal Description 24 13 1 Rules for Output Messages The NXDM module observe...

Page 1069: ...shown for reference only 0x1 R 0x02 Port Configuration Register PCR 1 Refer to NPC R W Development Control 1 DC1_n 0x2 R W 0x04 0x05 Development Control 2 DC2_n 0x3 R W 0x05 0x06 Watchpoint Trigger W...

Page 1070: ...e functions are controlled globally by the NPC port control register PCR Output port mode control 0 Reduced port mode configuration 1 Full port mode configuration 30 29 MCK_DIV1 MCK_DIV nexus message...

Page 1071: ...EOC bits in DC1 must be programmed to trigger EVTO on watchpoint occurrence for the EWC bits to have any effect EVTO Watchpoint Configuration 00000000 No watchpoints trigger EVTO 1XXXXXXX Reserved X1X...

Page 1072: ...1 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RWT1 RWT2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RC1 RC2 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F...

Page 1073: ...s 0 internal range accesses to DTSA and DTEA addresses will be traced When the range control bit is 1 external range accesses to DTSA and DTEA will not be traced Access R W 31 30 29 28 27 26 25 24 23...

Page 1074: ...Description Field Description 31 30 BWE1 Breakpoint watchpoint 1 enable 00 Internal Nexus watchpoint 1 disabled 01 10 Reserved 11 Internal Nexus watchpoint 1 enabled 29 28 BRW1 Breakpoint watchpoint 1...

Page 1075: ...and system reset de assertion after the JTAG DID register has been read by the tool Table 24 53 BWC2 Field Description Field Description 31 30 BWE2 Breakpoint watchpoint 2 enable 00Internal Nexus wat...

Page 1076: ...er VRC and POR Module 24 14 2 11 2 Enabling the NXDM TAP Controller Assertion of a power on reset signal or assertion of the JCOMP pin resets all TAP controllers on the device Upon exit from the test...

Page 1077: ...DR then shifts the data in or out of the JTAG port lsb first a During a read access data is latched from the selected Nexus register when the JTAG state machine passes through the capture DR state b...

Page 1078: ...ace Date Write Message 6 6 TCODE Fixed TCODE number 5 4 4 SRC Fixed Source processor identifier multiple Nexus configuration 3 3 DSZ Fixed Data size refer to Table 24 58 1 32 U ADDR Variable Unique po...

Page 1079: ...onfiguration 4 4 WPHIT Fixed Number indicating watchpoint sources Table 24 57 Error Code ECODE Encoding TCODE 8 Error Code ECODE Description 00000 Reserved 00001 Reserved 00010 Data Trace overrun 0001...

Page 1080: ...essages contain the data write read value and the address of the write read access relative to the previous data trace message Data write message and data read message information is messaged out in t...

Page 1081: ...ith sync message occurred Upon assertion of the Event In EVTI pin the first data trace message will be a synchronization message if the eic bits of the dc register have enabled this feature Upon data...

Page 1082: ...read w sync message Queue Overrun An error message occurs when a new message cannot be queued due to the message queue being full The FIFO will discard messages until it has completely emptied the que...

Page 1083: ...idates to be traced 24 14 5 4 5 System Bus Cycle Special Cases 24 14 5 5 Data Trace Timing Diagrams 8 MDO configuration Data trace timing for the NXDM is the same as for the NZ6C3 Refer to Section 24...

Page 1084: ...f messages attempted to be queued while the FIFO was being emptied If only a watchpoint message attempts to enter the queue while it is being emptied the error message will incorporate the watchpoint...

Page 1085: ...ownership flow 2 When the periodic 255 OTM message counter expires after 255 queued messages without an OTM an OTM will be sent The data will be sent from either the latched OTR data or the latched p...

Page 1086: ...put Output Subsystem eMIOS 0xC3FA_0000 Page A 25 Enhanced Time Processing Unit eTPU 0xC3FC_0000 Page A 26 Peripheral Bridge B PBRIDGEB 0xFFF0_0000 Page A 31 System Bus Crossbar Switch XBAR 0xFFF0_4000...

Page 1087: ...t Base 0x0044 Peripheral bridge A off platform peripheral access control register 2 PBRIDGEA_OPACR2 32 bit Base 0x0048 Reserved Base 0x004C 0xC3F7_FFFF Frequency Modulated Phase Locked Loop FMPLL Chap...

Page 1088: ...ace Unit FLASH Chapter 13 Flash Memory 0xC3F8_8000 Module configuration register FLASH_MCR 32 bit Base 0x0000 Low mid address space block locking register FLASH_LMLR 32 bit Base 0x0004 High address sp...

Page 1089: ...Pad configuration register 5 ADDR 9 SIU_PCR5 16 bits Base 0x004A Pad configuration register 6 ADDR 10 SIU_PCR6 16 bits Base 0x004C Pad configuration register 7 ADDR 11 SIU_PCR7 16 bits Base 0x004E Pad...

Page 1090: ..._PCR35 16 bits Base 0x0086 Pad configuration register 36 DATA 8 SIU_PCR36 16 bits Base 0x0088 Pad configuration register 37 DATA 9 SIU_PCR37 16 bits Base 0x008A Pad configuration register 38 DATA 10 S...

Page 1091: ...er 69 TS SIU_PCR69 16 bits Base 0x00CA Pad configuration register 70 TA SIU_PCR70 16 bits Base 0x00CC Pad configuration register 71 TEA SIU_PCR71 16 bits Base 0x00CE Pad configuration register 72 BR S...

Page 1092: ...PCSA 5 SIU_PCR101 16 bits Base 0x010A Pad configuration register 102 SCKB SIU_PCR102 16 bits Base 0x010C Pad configuration register 103 SINB SIU_PCR103 16 bits Base 0x010E Pad configuration register...

Page 1093: ..._PCR132 16 bits Base 0x0148 Pad configuration register 133 eTPU A 19 SIU_PCR133 16 bits Base 0x014A Pad configuration register 134 eTPU A 20 SIU_PCR134 16 bits Base 0x014C Pad configuration register 1...

Page 1094: ...R197 16 bits Base 0x01CA Pad configuration register 198 eMIOS19 SIU_PCR198 16 bits Base 0x01CC Pad configuration register 199 eMIOS20 SIU_PCR199 16 bits Base 0x01CE Pad configuration register 200 eMIO...

Page 1095: ...SIU_PCR228 16 bits Base 0x0208 Pad configuration register 229 CLKOUT SIU_PCR229 16 bits Base 0x020A Pad configuration register 230 RSTOUT SIU_PCR230 16 bits Base 0x020C Reserved Base 0x020E 0x23F Pad...

Page 1096: ...figuration register 285 SIU_PCR285 16 bits Base 0x27A Pad configuration register 286 SIU_PCR286 16 bits Base 0x27C Pad configuration register 287 SIU_PCR287 16 bits Base 0x27E Pad configuration regist...

Page 1097: ...U_GPDO17 8 bits Base 0x0611 GPIO pin data output register 18 SIU_GPDO18 8 bits Base 0x0612 GPIO pin data output register 19 SIU_GPDO19 8 bits Base 0x0613 GPIO pin data output register 20 SIU_GPDO20 8...

Page 1098: ...r 49 SIU_GPDO49 8 bits Base 0x0631 GPIO pin data output register 50 SIU_GPDO50 8 bits Base 0x0632 GPIO pin data output register 51 SIU_GPDO51 8 bits Base 0x0633 GPIO pin data output register 52 SIU_GP...

Page 1099: ...r 81 SIU_GPDO81 8 bits Base 0x0651 GPIO pin data output register 82 SIU_GPDO82 8 bits Base 0x0652 GPIO pin data output register 83 SIU_GPDO83 8 bits Base 0x0653 GPIO pin data output register 84 SIU_GP...

Page 1100: ...SIU_GPDO113 8 bits Base 0x0671 GPIO pin data output register 114 SIU_GPDO114 8 bits Base 0x0672 GPIO pin data output register 115 SIU_GPDO115 8 bits Base 0x0673 GPIO pin data output register 116 SIU_...

Page 1101: ...5 SIU_GPDO145 8 bits Base 0x0691 GPIO pin data output register 146 SIU_GPDO146 8 bits Base 0x0692 GPIO pin data output register 147 SIU_GPDO147 8 bits Base 0x0693 GPIO pin data output register 148 SIU...

Page 1102: ...7 SIU_GPDO177 8 bits Base 0x06B1 GPIO pin data output register 178 SIU_GPDO178 8 bits Base 0x06B2 GPIO pin data output register 179 SIU_GPDO179 8 bits Base 0x06B3 GPIO pin data output register 180 SIU...

Page 1103: ...ts Base 0x06D0 GPIO pin data output register 209 SIU_GPDO209 8 bits Base 0x06D1 GPIO pin data output register 210 SIU_GPDO210 8 bits Base 0x06D2 GPIO pin data output register 211 SIU_GPDO211 8 bits Ba...

Page 1104: ...er 26 SIU_GPDI26 8 bits Base 0x081A GPIO pin data input register 27 SIU_GPDI27 8 bits Base 0x081B GPIO pin data input register 28 SIU_GPDI28 8 bits Base 0x081C GPIO pin data input register 29 SIU_GPDI...

Page 1105: ...er 58 SIU_GPDI58 8 bits Base 0x083A GPIO pin data input register 59 SIU_GPDI59 8 bits Base 0x083B GPIO pin data input register 60 SIU_GPDI60 8 bits Base 0x083C GPIO pin data input register 61 SIU_GPDI...

Page 1106: ...U_GPDI90 8 bits Base 0x085A GPIO pin data input register 91 SIU_GPDI91 8 bits Base 0x085B GPIO pin data input register 92 SIU_GPDI92 8 bits Base 0x085C GPIO pin data input register 93 SIU_GPDI93 8 bit...

Page 1107: ...22 SIU_GPDI122 8 bits Base 0x087A GPIO pin data input register 123 SIU_GPDI123 8 bits Base 0x087B GPIO pin data input register 124 SIU_GPDI124 8 bits Base 0x087C GPIO pin data input register 125 SIU_G...

Page 1108: ...54 SIU_GPDI154 8 bits Base 0x089A GPIO pin data input register 155 SIU_GPDI155 8 bits Base 0x089B GPIO pin data input register 156 SIU_GPDI156 8 bits Base 0x089C GPIO pin data input register 157 SIU_G...

Page 1109: ...86 SIU_GPDI186 8 bits Base 0x08BA GPIO pin data input register 187 SIU_GPDI187 8 bits Base 0x08BB GPIO pin data input register 188 SIU_GPDI188 8 bits Base 0x08BC GPIO pin data input register 189 SIU_G...

Page 1110: ...put select register SIU_DISR 32 bits Base 0x0908 Reserved Base 0x090C 0x097F Chip configuration register SIU_CCR 32 bits Base 0x0980 External clock control register SIU_ECCR 32 bits Base 0x0984 Compar...

Page 1111: ...32 bit Base 0x0024 eTPU A time base 2 ETPU_TB2R_A 32 bit Base 0x0028 eTPU A STAC bus interface configuration register ETPU_REDCR_A 32 bit Base 0x002C Reserved Base 0x0050 0x01FF eTPU A channel interr...

Page 1112: ...bit Base 0x0430 eTPU A channel 3 status and control register ETPU_C3SCR_A 32 bit Base 0x0434 eTPU A channel 3 host service request register ETPU_C3HSRR_A 32 bit Base 0x0438 Reserved Base 0x043C 0x043F...

Page 1113: ...Base 0x04B0 eTPU A channel 11 status and control register ETPU_C11SCR_A 32 bit Base 0x04B4 eTPU A channel 11 host service request register ETPU_C11HSRR_A 32 bit Base 0x04B8 Reserved Base 0x04BC 0x04BF...

Page 1114: ...32 bit Base 0x0530 eTPU A channel 19 status and control register ETPU_C19SCR_A 32 bit Base 0x0534 eTPU A channel 19 host service request register ETPU_C19HSRR_A 32 bit Base 0x0538 Reserved Base 0x053...

Page 1115: ...32 bit Base 0x05B0 eTPU A channel 27 status and control register ETPU_C27SCR_A 32 bit Base 0x05B4 eTPU A channel 27 host service request register ETPU_C27HSRR_A 32 bit Base 0x05B8 Reserved Base 0x05BC...

Page 1116: ...GEB_OPACR1 32 bit Base 0x0044 Peripheral bridge B off platform peripheral access control register 2 PBRIDGEB_OPACR2 32 bit Base 0x0048 Peripheral bridge B off platform peripheral access control regist...

Page 1117: ...ftware watchdog timer interrupt register ECSM_SWTIR 1 8 bit Base 0x001F Reserved Base 0x0020 0x0023 FEC Burst Optimization Master Control register FBOMCR 32 bit Base 0x0024 Reserved Base 0x0028 0x0042...

Page 1118: ...ter EDMA_CERQR 8 bit Base 0x0019 Set enable error interrupt register EDMA_SEEIR 8 bit Base 0x001A Clear enable error interrupt request register EDMA_CEEIR 8 bit Base 0x001B Clear interrupt request reg...

Page 1119: ...ter 20 EDMA_CPR20 8 bit Base 0x0114 Channel priority register 21 EDMA_CPR21 8 bit Base 0x0115 Channel priority register 22 EDMA_CPR22 8 bit Base 0x0116 Channel priority register 23 EDMA_CPR23 8 bit Ba...

Page 1120: ...egister 52 EDMA_CPR52 8 bit Base 0x0134 Channel priority register 53 EDMA_CPR53 8 bit Base 0x0135 Channel priority register 54 EDMA_CPR54 8 bit Base 0x0136 Channel priority register 55 EDMA_CPR55 8 bi...

Page 1121: ...TCD19 256 bit Base 0x1260 Transfer control descriptor register 20 TCD20 256 bit Base 0x1280 Transfer control descriptor register 21 TCD21 256 bit Base 0x12A0 Transfer control descriptor register 22 T...

Page 1122: ...ster 50 TCD50 256 bit Base 0x1640 Transfer control descriptor register 51 TCD51 256 bit Base 0x1660 Transfer control descriptor register 52 TCD52 256 bit Base 0x1680 Transfer control descriptor regist...

Page 1123: ...bit Base 0x0027 Reserved Base 0x0028 0x003F Priority select register 0 INTC_PSR0 8 bit Base 0x0040 Priority select register 1 INTC_PSR1 8 bit Base 0x0041 Priority select register 2 INTC_PSR2 8 bit Ba...

Page 1124: ...register 31 INTC_PSR31 8 bit Base 0x005F Priority select register 32 INTC_PSR32 8 bit Base 0x0060 Priority select register 33 INTC_PSR33 8 bit Base 0x0061 Priority select register 34 INTC_PSR34 8 bit...

Page 1125: ...register 63 INTC_PSR63 8 bit Base 0x007F Priority select register 64 INTC_PSR64 8 bit Base 0x0080 Priority select register 65 INTC_PSR65 8 bit Base 0x0081 Priority select register 66 INTC_PSR66 8 bit...

Page 1126: ...NTC_PSR95 8 bit Base 0x009F Priority select register 96 INTC_PSR96 8 bit Base 0x00A0 Priority select register 97 INTC_PSR97 8 bit Base 0x00A1 Priority select register 98 INTC_PSR98 8 bit Base 0x00A2 P...

Page 1127: ...ster 127 INTC_PSR127 8 bit Base 0x00BF Priority select register 128 INTC_PSR128 8 bit Base 0x00C0 Priority select register 129 INTC_PSR129 8 bit Base 0x00C1 Priority select register 130 INTC_PSR130 8...

Page 1128: ...ster 159 INTC_PSR159 8 bit Base 0x00DF Priority select register 160 INTC_PSR160 8 bit Base 0x00E0 Priority select register 161 INTC_PSR161 8 bit Base 0x00E1 Priority select register 162 INTC_PSR162 8...

Page 1129: ...ster 191 INTC_PSR191 8 bit Base 0x00FF Priority select register 192 INTC_PSR192 8 bit Base 0x0100 Priority select register 193 INTC_PSR193 8 bit Base 0x0101 Priority select register 194 INTC_PSR194 8...

Page 1130: ...ster 223 INTC_PSR223 8 bit Base 0x011F Priority select register 224 INTC_PSR224 8 bit Base 0x0120 Priority select register 225 INTC_PSR225 8 bit Base 0x0121 Priority select register 226 INTC_PSR226 8...

Page 1131: ...ster 255 INTC_PSR255 8 bit Base 0x013F Priority select register 256 INTC_PSR256 8 bit Base 0x0140 Priority select register 257 INTC_PSR257 8 bit Base 0x0141 Priority select register 258 INTC_PSR258 8...

Page 1132: ...se 0x015E Priority select register 287 INTC_PSR287 8 bit Base 0x015F Priority select register 288 INTC_PSR288 8 bit Base 0x0160 Priority select register 289 INTC_PSR289 8 bit Base 0x0161 Priority sele...

Page 1133: ...C_RFPR3 32 bit Base 0x003C Result FIFO pop register 4 EQADC_RFPR4 32 bit Base 0x0040 Result FIFO pop register 5 EQADC_RFPR5 32 bit Base 0x0044 Reserved Base 0x0048 0x004F CFIFO control register 0 EQAD...

Page 1134: ...CFIFO transfer counter register 5 EQADC_CFTCR5 16 bit Base 0x009A Reserved Base 0x009C 0x009F CFIFO status snapshot register 0 EQADC_CFSSR0 32 bit Base 0x00A0 CFIFO status snapshot register 1 EQADC_CF...

Page 1135: ...32 bit Base 0x020C Reserved Base 0x0210 0x023F CFIFO 5 register 0 EQADC_CF5R0 32 bit Base 0x0240 CFIFO 5 register 1 EQADC_CF5R1 32 bit Base 0x0244 CFIFO 5 register 2 EQADC_CF5R2 32 bit Base 0x0248 CF...

Page 1136: ...ADC_RF5R1 32 bit Base 0x0444 RFIFO 5 register 2 EQADC_RF5R2 32 bit Base 0x0448 RFIFO 5 register 3 EQADC_RF5R3 32 bit Base 0x044C Reserved Base 0x0450 0x07FF ADC0 control register ADC0_CR No memory map...

Page 1137: ...2 bit Base 0x003C Transmit FIFO registers 1 DSPIx_TXFR1 32 bit Base 0x0040 Transmit FIFO registers 2 DSPIx_TXFR2 32 bit Base 0x0044 Transmit FIFO registers 3 DSPIx_TXFR3 32 bit Base 0x0048 Reserved Ba...

Page 1138: ...gister CANx_CR 32 bit Base 0x0004 Free running timer register CANx_TIMER 32 bit Base 0x0008 Reserved Base 0x000C 0x000F Receive global mask register CANx_RXGMASK 32 bit Base 0x0010 Receive buffer 14 m...

Page 1139: ...0x0180 Message buffer 17 MB17 16 bit Base 0x0190 Message buffer 18 MB18 16 bit Base 0x01A0 Message buffer 19 MB19 16 bit Base 0x01B0 Message buffer 20 MB20 16 bit Base 0x01C0 Message buffer 21 MB21 16...

Page 1140: ...MB47 16 bit Base 0x0370 Message buffer 48 MB48 16 bit Base 0x0380 Message buffer 49 MB49 16 bit Base 0x0390 Message buffer 50 MB50 16 bit Base 0x03A0 Message buffer 51 MB51 16 bit Base 0x03B0 Message...

Page 1141: ...urpose Registers SPRG0 Special Purpose Register 0 272 SPRG1 Special Purpose Register 1 273 SPRG2 Special Purpose Register 2 274 SPRG3 Special Purpose Register 3 275 SPRG4 Special Purpose Register 4 27...

Page 1142: ...rrupt Vector Offset Register 15 415 IVOR32 Interrupt Vector Offset Register 32 528 IVOR33 Interrupt Vector Offset Register 33 529 IVOR34 Interrupt Vector Offset Register 34 530 Processor Control Regis...

Page 1143: ...nt Registers MAS0 MMU Assist Register 0 624 MAS1 MMU Assist Register 1 625 MAS2 MMU Assist Register 2r 626 MAS3 MMU Assist Register 3 627 MAS4 MMU Assist Register 4 628 MAS6 MMU Assist Register 6 630...

Page 1144: ...ose Registers N A Special Purpose Registers SPRG4 Special Purpose Register 4 260 SPRG5 Special Purpose Register 5 261 SPRG6 Special Purpose Register 6 262 SPRG7 Special Purpose Register 7 263 USPRG0 U...

Page 1145: ...MPC5565 Register Map MPC5565 Microcontroller Reference Manual Rev 1 0 A 60 Freescale Semiconductor...

Page 1146: ...alibration assembled devices is detailed in Figure B 1 Freescale produced VertiCal bases use the calibration assembled MPC5500 device mounted on a small circuit board with a footprint which is compati...

Page 1147: ...Assembly Figure B 2 VertiCal Base VertiCal compliant top board VertiCal base Application production PCB VertiCal connector system Calibration packaged MPC5500 device Production packaged sized 23mm 324...

Page 1148: ...the flexibility of increasing the addressing range or the number of chip selects Devices that support less than four calibration chip selects can extend the contiguous calibration addressing range by...

Page 1149: ...ted by the master to indicate that this transaction is targeted for a particular calibration memory bank The calibration chip selects are driven by the EBI CAL_CS n is driven in the same clock as the...

Page 1150: ...in the drive strength the CLKOUT timing and hence the timing of the non calibration bus can have minor differences with a calibration tool from the production package B 5 Power Supplies The signals t...

Page 1151: ...SRAM Top Board is added onto the VertiCal connector This allows the engine calibrator to modify settings in SRAM possibly using the Nexus interface or even by using the SCI port or a CAN interface Ref...

Page 1152: ...bration MPC5565 Microcontroller Reference Manual Rev 1 0 Freescale Semiconductor B 7 B 8 Document Revision History Table B 3 Changes Between MPC5565RM Revisions 0 1 and 1 No changes since the last rel...

Page 1153: ...Calibration MPC5565 Microcontroller Reference Manual Rev 1 0 B 8 Freescale Semiconductor...

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