Freescale Semiconductor MPC5565, Reference Manual

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Frequency Modulated Phase Locked Loop and System Clocks (FMPLL)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
11-10 Freescale Semiconductor
Figure 11-7. Crystal Oscillator Network
In crystal reference mode, the FMPLL can generate a frequency modulated clock or a non-modulated
clock (locked on a single frequency). The modulation rate, modulation depth, output clock divide ratio
(RFD), and whether the FMPLL is modulating or not can be programmed by writing to the FMPLL
registers. Crystal reference is the default clock mode for the 324 pin package. It is not necessary to force
PLLCFG[0:1] to enter this mode.
Tying the PLLCFG[2] signal low is required to operate in the 8–20 MHz range. Refer to
FMPLL_SYNCR[PREDIV].
11.1.4.2 External Reference Mode
This external reference mode functions the same as crystal reference mode except that EXTAL_EXTCLK
is driven by an external clock generator rather than a crystal oscillator. Also, the input frequency range
(F
ref_ext
) in external reference mode is the same as the input frequency reference range (F
ref-crystal
) in the
crystal reference mode; frequency modulation is available. To enter external reference mode, the default
FMPLL configuration must be overridden by following the procedure outlined in
Section 11.1.4, “FMPLL
Modes of Operation .” A block diagram illustrating external reference mode is shown in Figure 11-3 .
V
SSSYN
C2
EXTAL XTAL V
SSSYN
C1
Crystal
RF
1
On chip
1
For an 8–20 MHz crystal, the resistor must be 1–2.8K
Ω
. For a 40 MHz crystal, the resistor must
be approximately 500
Ω
. The exact value depends on the crystal characteristics, thus consult the
crystal manufacturer.
Oscillator