Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Time Processing Unit (eTPU)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 17-17
17.4.3 System Configuration Registers
17.4.3.1 eTPU Module Configuration Register (ETPU_MCR)
This register is global to both eTPU engines, and resides in the shared BIU. ETPU_MCR gathers global
configuration and status in the eTPU system, including global exception. It is also used for configuring the
SCM (shared code memory) operation and test.
Base + 0x0001_0000–
Base + 0x0001_2FFF
SCM Shared Code Memory
2
12 KB
Base + 0x0001_3000–
Base + 0x0001_FFFF
— Reserved —
1
Parameter sign extension access area. Refer to the eTPU Reference Manual .
2
SCM access is only available under certain conditions when ETPU_MCR[VIS] = 1. The SCM can only be written in 32-bit
accesses.
Address: Base + 0x0000_0000 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 MGEA MGEB ILFA 0 0 0 0 SCMSIZE
W GEC
Reset 0 0 0 0 0 0 0 0 0 0 0 SCMSIZE
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 0 0 0 0
SCMM
ISF
SC
M
MISEN
0 0
VIS
0 0 0 0 0
GTBE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 17-5. eTPU Module Configuration Register (ETPU_MCR)
Table 17-6. ETPU_MCR Field Descriptions
Field Description
0
GEC
Global exception clear. Negates global exception request and clears global exception status bits MGEA, MGEB,
ILFA, ILFB and SCMMISF. A read always returns 0. Writes have the following effect:
0 Keep global exception request and status bits ILFA, ILFB, MGEA, MGEB, and SCMMISF as is.
1 Negate global exception, clear status bits ILFA, ILFB, MGEA, MGEB, and SCMMISF.
GEC works the same way with either one or both engines in stop mode.
1–3 Reserved.
Table 17-5. Detailed Memory Map (continued)
Address Register Name Register Description Bits