Freescale Semiconductor MPC5565, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 19-3
The DSPI has three configurations:
• Serial peripheral interface (SPI) configuration where the DSPI operates as an SPI with support for
queues.
• Deserial serial interface (DSI) configuration where the DSPI serializes eTPU and eMIOS output
channels and deserializes the received data by placing the data on the eTPU and eMIOS input
channels and as inputs to the external interrupt request submodule of the SIU.
• Combined serial interface (CSI) configuration where the DSPI operates in both SPI and DSI
configurations interleaving DSI frames with SPI frames, giving priority to SPI frames.
For queued operations the SPI queues reside in internal SRAM which is external to the DSPI. Data
transfers between the queues and the DSPI FIFOs are accomplished through the use of the eDMA
controller or through host software.
Figure 19-2 shows a DSPI with external queues in internal SRAM.
Figure 19-2. DSPI with Queues and eDMA
19.1.3 Features
The DSPI supports these SPI features:
• Full-duplex, three-wire synchronous transfers
• Master and slave mode
• Buffered transmit and receive operation using the TX and RX FIFOs, with depths of four entries
• Visibility into TX and RX FIFOs for ease of debugging
• FIFO bypass mode for low-latency updates to SPI queues
Internal SRAM
TX queue
RX queue
Address/control
TX FIFO
DSPI
RX FIFO
RX data
TX data
TX data RX data
Shift register
eDMA controller
Address/control
or host CPU