Freescale Semiconductor MPC5565, Reference Manual

Page: 720 / 1153

Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 18-21
Table 18-11. EQADC_IDCR n Field Descriptions
Field Description
0
NCIE n
Non-coherency interrupt enable n . Enables the eQADC to generate an interrupt request when the corresponding
NCF n , described in Section 18.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn) ,” is
asserted.
0 Disable non-coherency interrupt request
1 Enable non-coherency interrupt request
1
TORIE n
Trigger overrun interrupt enable n . Enables the eQADC to generate an interrupt request when the corresponding
TORF n (described in Section 18.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn) ”) is
asserted.
Apart from generating an independent interrupt request for a CFIFO
n trigger overrun event, the eQADC also
provides a combined interrupt at which the result FIFO overflow interrupt, the command FIFO underflow interrupt,
and the command FIFO trigger overrun interrupt requests of all CFIFOs are ORed. When RFOIE
n , CFUIE n , and
TORIE n are all asserted, this combined interrupt request is asserted whenever one of the following 18 flags becomes
asserted: RFOF n , CFUF n , and TORF n (assuming that all interrupts are enabled). Refer to Section 18.4.7, “eQADC
eDMA/Interrupt Request
,”
for details.
0 Disable trigger overrun interrupt request
1 Enable trigger overrun interrupt request
2
PIE n
Pause interrupt enable n . Enables the eQADC to generate an interrupt request when the corresponding PFx in
EQADC_FISRn is asserted. Refer to Section 18.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5
(EQADC_FISRn) .”
0 Disable pause interrupt request
1 Enable pause interrupt request
3
EOQIE n
End-of-queue interrupt enable n . Enables the eQADC to generate an interrupt request when the corresponding
EOQF n in EQADC_FISRn is asserted. Refer to Section 18.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5
(EQADC_FISRn) .”
0 Disable end of queue interrupt request.
1 Enable end of queue
interrupt request.
4
CFUIE n
CFIFO underflow interrupt enable n . Enables the eQADC to generate an interrupt request when the corresponding
CFUF n in EQADC_FISRn is asserted.
Apart from generating an independent interrupt request for a CFIFO n underflow event, the eQADC also provides a
combined interrupt at which the result FIFO overflow interrupt, the command FIFO underflow interrupt, and the
command FIFO trigger overrun interrupt requests of all CFIFOs are ORed. When RFOIE
n , CFUIE n , and TORIE n
are all asserted, this combined interrupt request is asserted whenever one of the following 18 flags becomes
asserted: RFOF
n , CFUF n , and TORF n (assuming that all interrupts are enabled). Refer to Section 18.4.7, “eQADC
eDMA/Interrupt Request ,” for details.
0 Disable underflow interrupt request
1 Enable underflow interrupt request
5 Reserved.
6
CFFE n
CFIFO fill enable n . Enables the eQADC to generate an interrupt request (CFFS n is asserted) or eDMA request
(CFFS n is negated) when CFFF n in EQADC_FISRn is asserted. Refer to Section 18.3.2.8, “eQADC FIFO and
Interrupt Status Registers 0–5 (EQADC_FISRn) .”
0 Disable CFIFO fill eDMA or interrupt request
1 Enable CFIFO fill eDMA or interrupt request
Note: CFFE n must not be negated while an eDMA transaction is in progress.
7
CFFS n
CFIFO fill select n . Selects if an eDMA or interrupt request is generated when CFFF n in EQADC_FISRn (Refer to
Section 18.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn) ”
)
is asserted. If CFFE n is
asserted, the eQADC generates an interrupt request when CFFS n is negated, or it generates an eDMA request if
CFFS n is asserted.
0 Generate interrupt request to move data from the system memory to CFIFO n .
1 Generate eDMA request to move data from the system memory to CFIFO n .
Note: CFFS n must not be negated while an eDMA transaction is in progress.