Freescale Semiconductor MPC5565, Reference Manual

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Preface
MPC5565 Microcontroller Reference Manual, Rev. 1.0
21-22 Freescale Semiconductor
21.3.3.9 Interrupt Masks Low Register (CAN x _IMRL)
CAN x _IMRL allows enabling or disabling any number of a range of 32 message buffer interrupts. It
contains one interrupt mask bit per buffer, enabling the CPU to determine which buffer generates an
interrupt after a successful transmission or reception (that is, when the corresponding IFRL bit is set).
21.3.3.10 Interrupt Flags High Register (CAN x _IFRH)
CAN x _IFRH defines the flags for 32 message buffer interrupts. It contains one interrupt flag bit per buffer.
Each successful transmission or reception sets the corresponding IFRH bit. If the corresponding IMRH bit
is set, an interrupt will be generated. The interrupt flag may be cleared by writing it to 1. Writing 0 has no
effect.
Table 21-13. CAN x _IMRH Field Descriptions
Field Description
0–31
BUF n M
Message buffer n mask. Enables or disables the respective FlexCAN2 message buffer (MB63 to MB32)
Interrupt.
0 The corresponding buffer Interrupt is disabled
1 The corresponding buffer Interrupt is enabled
Note: Setting or clearing a bit in the IMRH register can assert or negate an interrupt request, respectively.
Address: Base + 0x0028 Access: User R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R BUF
31M
BUF
30M BUF
29M BUF
28M BUF
27M BUF
26M BUF
25M BUF
24M BUF
23M BUF
22M BUF
21M BUF
20M BUF
19M BUF
18M BUF
17M BUF
16M
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R BUF
15M
BUF
14M BUF
13M BUF
12M BUF
11M BUF
10M BUF
09M BUF
08M BUF
07M BUF
06M BUF
05M BUF
04M BUF
03M BUF
02M BUF
01M BUF
00M
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 21-11. Interrupt Masks Low Register (CAN x _IMRL)
Table 21-14. CAN x _IMRL Field Descriptions
Field Description
0–31
BUF n M
Message buffer n mask. Enables or disables the respective FlexCAN2 message buffer (MB31 to MB0)
Interrupt.
0 The corresponding buffer Interrupt is disabled
1 The corresponding buffer Interrupt is enabled
Note: Setting or clearing a bit in the IMRL register can assert or negate an interrupt request, respectively.