Freescale Semiconductor MPC5565, Reference Manual

Page: 300 / 1153

Crossbar Switch (XBAR)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 7-3
7.1.4 Modes of Operation
7.1.4.1 Normal Mode
In normal mode, the XBAR provides the register interface and logic that controls crossbar switch
configuration.
7.1.4.2 Debug Mode
The XBAR operation in debug mode is identical to operation in normal mode.
7.2 Memory Map and Register Definition
The memory map for the XBAR program-visible registers is shown in Table 7-2 .
Table 7-2. XBAR Register Memory Map
Address Register Name Register Description Bits
Base = 0xFFF0_4000 XBAR_MPR0 Master priority register for slave port 0 32
Base + 0x0004–
Base +
0x000F
— Reserved —
Base + 0x0010 XBAR_SGPCR0 General-purpose control register for slave port 0 32
Base + 0x0014–
Base + 0x00FF
— Reserved —
Base + 0x0100 XBAR_MPR1 Master priority register for slave port 1 32
Base + 0x0104–
Base + 0x010F
— Reserved —
Base + 0x0110 XBAR_SGPCR1 General-purpose control register for slave port 1 32
Base + 0x0114–
Base + 0x02FF
— Reserved —
Base + 0x0300 XBAR_MPR3 Master priority register for slave port 3 32
Base + 0x0304–
Base + 0x030F
— Reserved —
Base + 0x0310 XBAR_SGPCR3 General-purpose control register for slave port 3 32
Base + 0x0314–
Base +
0x05FF
— Reserved —
Base + 0x0600 XBAR_MPR6 Master priority register for slave port 6 32
Base + 0x0604–
Base + 0x060F
— Reserved —
Base + 0x0610 XBAR_SGPCR6 General-purpose control register for slave port 6 32
Base + 0x0614–
Base +
0x06FF
— Reserved —
Base + 0x0700 XBAR_MPR7 Master priority register for slave port 7 32