Freescale Semiconductor MPC5565, Reference Manual

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Peripheral Bridge (PBRIDGE_A, PBRIDGE_B)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
5-12 Freescale Semiconductor
Write buffering is controllable on a per-master and per-peripheral basis. Enable write buffering for masters
and peripherals only when an error termination from the slave bus does not occur or is safe to ignore. When
write buffering is enabled, all accesses through the PBRIDGE must occur in sequence; bypassing buffered
writes is
not supported.
NOTE
Write buffering causes the processor core to believe that the write has
completed before it actually has completed in the peripheral. If write
buffering is enabled for a peripheral, the actual write takes an additional two
system clock cycles plus any additional system clock cycles that the register
needs. Most registers in the MPC5500 family delay the write by two clock
cycles, but some registers take longer. This early termination, as seen by the
processor core, can defeat the
mbar or msync instruction between the write
to clear a flag bit and the write to the INTC_EOIR. Therefore, if write
buffering is enabled for a peripheral that has a flag bit, insert instructions
between the
mbar or msync instruction and the write to the INTC_EOIR
that consumes at least the number of system clock cycles that the actual
write is delayed.
Refer to Section 10.4.3.1.2, “End-of-Interrupt Exception Handler .”
5.4.2.1 Read Cycles
Read accesses are possible with the PBRIDGE when the requested access size is 32-bits or smaller, and is
not misaligned across a 32-bit boundary. 64-bit data reads (not instruction) are not supported.
5.4.2.2 Write Cycles
Write accesses are possible with the PBRIDGE when the requested access size is 32-bits or smaller.
Misaligned writes that cross a 32-bit boundary are not supported. 64-bit data writes (not instruction) are
not supported.
5.4.2.3 Buffered Write Cycles
Single clock write responses to the system bus are possible with the PBRIDGE when the requested write
access is bufferable. If the requested access does not violate the permissions check, and if both master and
peripheral are enabled for buffering writes, the PBRIDGE internally buffers the write cycle. The write
cycle is terminated early with zero system bus wait states. The access proceeds normally on the slave
interface, but error responses are ignored.
All accesses are initiated and completed in order on the slave interface, regardless of buffering. If the
buffer is full, a following write cycle stalls until it can either be buffered (if bufferable) or can be initiated.
If the buffer has valid entries, a following read cycle stalls until the buffer is emptied and the read cycle
can be completed.