Interrupt Controller (INTC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
10-26
Freescale Semiconductor
stored onto the context stack. Likewise at the end of the interrupt exception handler, the priority does not
need to be loaded from the context stack and stored into the INTC_CPR.
The PRI value in the INTC_CPR is pushed onto the LIFO when the INTC_IACKR is read in software
vector mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode.
The priority is popped into PRI in the INTC_CPR whenever the INTC_EOIR is written.
Although the INTC supports 16 priorities, an ISR executing with PRI in the INTC_CPR equal to 15 is not
preempted. Therefore, the LIFO supports the stacking of 15 priorities. However, the LIFO is only 14
entries deep. An entry for a priority of 0 is not needed because of how pushing onto a full LIFO and
popping an empty LIFO are treated. If the LIFO is pushed 15 or more times than it is popped, the priorities
first pushed are overwritten. A priority of 0 would be an overwritten priority. However, the LIFO pop zeros
if it is popped more times than it is pushed. Therefore, although a priority of 0 was overwritten, it is
regenerated with the popping of an empty LIFO.
The LIFO is not memory mapped.
10.4.3
Details on Handshaking with Processor
10.4.3.1
Software Vector Mode Handshaking
10.4.3.1.1
Acknowledging Interrupt Request to Processor
A timing diagram of the interrupt request and acknowledge handshaking in software vector mode, along
with the handshaking near the end of the interrupt exception handler, is shown in
. The INTC
examines the peripheral and software settable interrupt requests. When it finds an asserted peripheral or
software settable interrupt request with a higher priority than PRI in INTC current priority register
(INTC_CPR), it asserts the interrupt request to the processor. The INTVEC field in INTC interrupt
acknowledge register (INTC_IACKR) is updated with the preempting interrupt request’s vector when the
interrupt request to the processor is asserted. The INTVEC field retains that value until the next time the
interrupt request to the processor is asserted. The rest of the handshaking is described in
10.4.3.1.2
End-of-Interrupt Exception Handler
Before the interrupt exception handling completes, INTC end-of-interrupt register (INTC_EOIR) must be
written. When it is written, the LIFO is popped so that the preempted priority is restored into PRI of the
INTC_CPR. Before it is written, the peripheral or software settable flag bit must be cleared so that the
peripheral or software settable interrupt request is negated.
NOTE
To ensure proper operation across all Power Architecture MCUs, execute an
MBAR
or
MSYNC
instruction between the access to clear the flag bit and the
write to the INTC_EOIR.
When returning from the preemption, the INTC does not search for the peripheral or software settable
interrupt request whose ISR was preempted. Depending on how much the ISR progressed, that interrupt
request can no longer be asserted. When PRI in INTC_CPR is lowered to the priority of the preempted
Summary of Contents for MPC5565
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