Freescale Semiconductor MPC5565, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 19-55
Table 19-27 shows an example of the computed the t
PASC
delay.
19.4.7 Transfer Formats
The SPI serial communication is controlled by the serial communications clock (SCK x ) signal and the
PCS x signals. The SCK x signal provided by the master device synchronizes shifting and sampling of the
data by the SIN x and SOUT x pins. The PCS x signals serve as enable signals for the slave devices.
When the DSPI is the bus master, the CPOL and CPHA bits in the DSPI clock and transfer attributes
registers (DSPI
x _CTAR n ) select the polarity and phase of the serial clock, SCK x . The polarity bit selects
the idle state of the SCK x . The clock phase bit selects if the data on SOUT x is valid before or on the first
SCK x edge.
When the DSPI is the bus slave, CPOL and CPHA bits in the DSPI x _CTAR0 (SPI slave mode) or
DSPI x _CTAR1 (DSI slave mode) select the polarity and phase of the serial clock. Even though the bus
slave does not control the SCK signal, clock polarity, clock phase and number of bits to transfer must be
identical for the master device and the slave device to ensure proper transmission.
The DSPI supports four different transfer formats:
• Classic SPI with CPHA = 0
• Classic SPI with CPHA = 1
• Modified transfer format with CPHA = 0
• Modified transfer format with CPHA = 1
A modified transfer format is supported to allow for high-speed communication with peripherals that
require longer setup times. The DSPI can sample the incoming data later than halfway through the cycle
to give the peripheral more setup time. The MTFE bit in the DSPI
x _MCR selects between classic SPI
format and modified transfer format. The classic SPI formats are described in Section 19.4.7.1, “Classic
SPI Transfer Format (CPHA = 0) ” and Section 19.4.7.2, “Classic SPI Transfer Format (CPHA = 1) .” The
modified transfer formats are described in Section 19.4.7.3, “Modified SPI/DSI Transfer Format (MTFE
= 1, CPHA = 0) ” and Section 19.4.7.4, “Modified SPI/DSI Transfer Format (MTFE = 1, CPHA = 1) .”
In the SPI and DSI configurations, the DSPI provides the option of keeping the PCS signals asserted
between frames. Refer to
Section 19.4.7.5, “Continuous Selection Format ” for details.
Table 19-27. Peripheral Chip Select Strobe Negate Computation Example
PASC Prescaler
f
SYS
Delay after Transfer
0b11 7 100 MHz 70.0 ns