Freescale Semiconductor MPC5565, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 19-59
Figure 19-34 shows the modified transfer format for CPHA = 0. Only the condition where CPOL = 0 is
illustrated. The delayed master sample points are indicated with a lighter shaded arrow.
Figure 19-34. DSPI Modified Transfer Format (MTFE = 1, CPHA = 0, f
SCK
=
f
SYS
/ 4)
19.4.7.4 Modified SPI/DSI Transfer Format (MTFE = 1, CPHA = 1)
At the start of a transfer the DSPI asserts the PCS signal to the slave device. After the PCS to SCK delay
has elapsed the master and the slave put data on their SOUT pins at the first edge of SCK. The slave
samples the master SOUT signal on the even numbered edges of SCK. The master samples the slave
SOUT signal on the odd numbered SCK edges starting with the 3rd SCK edge. The slave samples the last
bit on the last edge of the SCK. The master samples the last slave SOUT bit one half SCK cycle after the
last edge of SCK. No clock edge is visible on the master SCK pin during the sampling of the last bit. The
SCK to PCS delay must be greater or equal to half of the SCK period.
NOTE
For the modified transfer format to operate correctly, you must thoroughly
analyze the SPI link timing budget.
t
CSC
= PCS to SCK delay.
t
ASC
= After SCK delay.
System clock
1 2 3 4 5 6
PCS
x
t
ASC
SCK
Master sample
Slave SOUT
Master SOUT
System clock
System clock
Slave sample
t
CSC