Freescale Semiconductor MPC5565, Reference Manual

Page: 134 / 1153

e200z6 Core Complex
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 3-27
10 WAM
Way access mode
0 = Disable way access is checked not enabled for replacement on an access
type are still checked for a cache hit for accesses of that type but are not
replaced by an access miss of that type.
1 = Ways not enabled for replacement on a particular access type (instruction
vs. data) via the WID and WDD fields are disabled and no lookup is
performed for accesses of that type. Selecting WAM = 1 helps minimize
power consumption.
Software must ensure that the instruction to data coherency is maintained
when using the power-saving feature of the WAM control. Cache must be
invalidated prior to changing the value of this bit. Use of a dcbf followed by
an icbi, msync, isync for modified lines which can be executed is required to
maintain proper operation.
11 CWM
Cache write mode
0 = Cache operates in writethrough mode
1 = Cache operates in copyback mode
When set to writethrough mode, the “W” page attribute from an optional MMU is
ignored and all writes are treated as writethrough required. When set, write
accesses are performed in copyback mode unless the “W” page attribute from
an optional MMU is set.
12 DPB
Disable push buffer
0 = Push buffer enabled
1 = Push buffer disabled
13 DSB
Disable store buffer
0 = store buffer enabled
1 = store buffer disabled
14 DSTRM
Disable streaming
0 = streaming is enabled
1 = streaming is disabled
15 CPE
Cache parity enable
0 = parity checking is disabled
1 = parity checking is enabled
16–20 — Reserved
21 CUL
Cache unable to lock
Indicates a lock set instruction was not effective in locking a cache line. This bit
is set by hardware on an “unable to lock” condition (other than lock overflows),
and will remain set until cleared by software writing 0 to this bit location.
22 CLO
Cache lock overflow
Indicates a lock overflow (overlocking) condition occurred. This bit is set by
hardware on an “overlocking” condition, and will remain set until cleared by
software writing 0 to this bit location.
Table 3-9. L1CSR0 Field Descriptions (continued)
Bits Name Description