Freescale Semiconductor MPC5565, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
19-4 Freescale Semiconductor
• Programmable transfer attributes on a per-frame basis
— Eight clock and transfer attribute registers
— Serial clock with programmable polarity and phase
— Programmable delays
– PCS to SCK delay
– SCK to PCS delay
– Delay between frames
— Programmable serial frame size of 4 to 16 bits, expandable with software control
— Continuously held chip select capability
• Six peripheral chip selects, expandable to 64 with external demultiplexer
• Deglitching support for up to 32 peripheral chip selects with external demultiplexer
• Two DMA conditions for SPI queues residing in RAM or flash
— TX FIFO is not full (TFFF)
— RX FIFO is not empty (RFDF)
• Six interrupt conditions:
– End of queue reached (EOQF)
– TX FIFO is not full (TFFF)
– Transfer of current frame complete (TCF)
– RX FIFO is not empty (RFDF)
– FIFO overrun (attempt to transmit with an empty TX FIFO or serial frame received while
RX FIFO is full) (RFOF)
– FIFO under flow (slave only and SPI mode, the slave is asked to transfer data when the TX
FIFO is empty) (TFUF)
• Modified SPI transfer formats for communication with slower peripheral devices
• Supports all functional modes from QSPI subblock of QSMCM (MPC500 family)
• Continuous serial communications clock (SCK)
When configured for DSI or CSI operation, the DSPI supports pin reduction through serialization and
deserialization.
• Serialized data sources
— eTPUA, and eMIOS output channels
— Memory-mapped register in the DSPI
• Deserialized data destinations
— eTPUA and eMIOS input channels
— SIU external interrupt request inputs
— Memory-mapped register in the DSPI