Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Direct Memory Access (eDMA)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 9-13
9.2.2.6 eDMA Clear Enable Request Register (EDMA_CERQR)
The EDMA_CERQR provides a simple memory-mapped mechanism to clear a given bit in the
EDMA_ERQRL to disable the DMA request for a given channel. The data value on a register write causes
the corresponding bit in the EDMA_ERQRL to be cleared. Setting bit 1 (CERQ
n ) provides a global clear
function, forcing the entire contents of the EDMA_ERQRL to be zeroed, disabling all DMA request
inputs. Reads of this register return all zeroes.
9.2.2.7 eDMA Set Enable Error Interrupt Register (EDMA_SEEIR)
The EDMA_SEEIR provides a simple memory-mapped mechanism to set a given bit in the
EDMA_EEIRL to enable the error interrupt for a given channel. The data value on a register write causes
the corresponding bit in the EDMA_EEIRL to be set. Setting bit 1 (SEEI
n ) provides a global set function,
forcing the entire contents of EDMA_EEIRL to be asserted. Reads of this register return all zeroes.
Table 9-6. EDMA_SERQR Field Descriptions
Field Descriptions
0 Reserved.
1–7
SERQ[0:6]
Set enable request.
0–31 Set corresponding bit in EDMA_ERQRL
32–63 Reserved
64–127 Set all bits in EDMA_ERQRH and EDMA_ERQRL
Note: Bit 2 (SERQ1) is not used.
Address: Base + 0x0019 Access: User W/O
0 1 2 3 4 5 6 7
R 0 0 0 0 0 0 0 0
W CERQ[0:6]
Reset 0 0 0 0 0 0 0 0
Figure 9-7. eDMA Clear Enable Request Register (EDMA_CERQR)
Table 9-7. EDMA_CERQR Field Descriptions
Field Description
0 Reserved.
1–7
CERQ[0:6]
Clear enable request.
0–31 Clear corresponding bit in EDMA_ERQRL
32–63 Reserved
64–127 Clear all bits in EDMA_ERQRH and EDMA_ERQRL
Note: Bit 2 (CERQ1) is not used.