Enhanced Time Processing Unit (eTPU)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
17-42
Freescale Semiconductor
Table 17-26. ETPU_C
n
SCR Field Descriptions
Field
Description
0
CIS
Channel interrupt status.
0 Channel has no pending interrupt to the device core.
1 Channel has a pending interrupt to the device core.
CIS is mirrored in the ETPU_CISR. For more information on ETPU_CISR and interrupts, refer to
“eTPU Channel Interrupt Status Register (ETPU_CISR)
,” and the
eTPU Reference Manual
.
The core must write 1 to clear CIS.
1
CIOS
Channel interrupt overflow status.
0 Interrupt overflow negated for this channel
1 Interrupt overflow asserted for this channel
CIOS is mirrored in the ETPU_CIOSR. For more information on the ETPU_CIOSR and interrupt overflow, refer to
Section 17.4.5.3, “eTPU Channel Interrupt Overflow Status Register (ETPU_CIOSR)
” and the
eTPU Reference
Manual
.
The core must write 1 to clear CIOS.
2–7
Reserved.
8
DTRS
Data transfer request status.
0 Channel has no pending data transfer request.
1 Channel has a pending data transfer request.
DTRS is mirrored in the ETPU_CDTRSR. For more information on the ETPU_CDTRSR and data transfer, refer to
Section 17.4.5.2, “eTPU Channel Data Transfer Request Status Register (ETPU_CDTRSR)
” and the
eTPU
Reference Manual
.
The core must write 1 to clear DTRS.
9
DTROS
Data transfer request overflow status.
0 Data transfer request overflow negated for this channel.
1 Data transfer request overflow asserted for this channel.
DTROS is mirrored in the ETPU_CDTROSR. Refer to
Section 17.4.5.4, “eTPU Channel Data Transfer Request
Overflow Status Register (ETPU_CDTROSR)
” and the
eTPU Reference Manual
for more information on
ETPU_CDTROSR and data transfer overflows.
The core must write 1 to clear DTROS.
10–15
Reserved.
16
IPS
Channel input pin state. Shows the current value of the filtered channel input signal state
17
OPS
Channel output pin state. Shows the current value driven in the channel output signal, including the effect of the
external output disable feature. If the channel input and output signals are connected to the same pad, OPS reflects
the value driven to the pad. This is not necessarily the actual pad value, which drives the value in the IPS bit.
18–29
Reserved.
30–31
FM
[0:1]
Channel function mode.
1
Each function can use this field for specific configuration. These bits can be tested by
microengine code.
1
These bits are equivalent to the TPU/TPU2/TPU3 host sequence (HSQ) bits.
Summary of Contents for MPC5565
Page 18: ...MPC5565 Microcontroller Reference Manual Devices Supported MPC5565 MPC5565 RM Rev 1 0 09 2007...
Page 34: ...MPC5565 Reference Manual Rev 1 0 Freescale Semiconductor 15...
Page 35: ...MPC5565 Reference Manual Rev 1 0 16 Freescale Semiconductor...
Page 553: ...Flash Memory MPC5565 Microcontroller Reference Manual Rev 1 0 13 38 Freescale Semiconductor...
Page 559: ...SRAM MPC5565 Microcontroller Reference Manual Rev 1 0 14 6 Freescale Semiconductor...
Page 973: ...Preface MPC5565 Microcontroller Reference Manual Rev 1 0 21 36 Freescale Semiconductor...
Page 1153: ...Calibration MPC5565 Microcontroller Reference Manual Rev 1 0 B 8 Freescale Semiconductor...
