Freescale Semiconductor MPC5565, Reference Manual

Page: 733 / 1153

Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
18-34 Freescale Semiconductor
18.3.2.13 eQADC SSI Receive Data Register (EQADC_SSIRDR)
The eQADC SSI receive data register (EQADC_SSIRDR) records the last message received from the
external device.
0b1010 12
0b1011 13
0b1100 14
0b1101 15
0b1110 16
0b1111 17
1
If the system clock is divided by a odd number
then the serial clock has a duty cycle different
from 50%.
Address: Base + 0x0B8 Access: Read
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R RDV 0 0 0 0 0 R_DATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R R_DATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 18-16. eQADC SSI Receive Data Register (EQADC_SSIRDR)
Table 18-22. EQADC_SSIRDR Field Descriptions
Field Description
0
RDV
Receive data valid. Indicates if the last received data is valid. This bit is cleared automatically whenever the
EQADC_SSIRDR is read. Writes have no effect.
0 Receive data is not valid.
1 Receive data is valid.
1–5 Reserved.
6–31
R_DATA
[0:25]
eQADC receive DATA. Contains the last result message that was shifted in. Writes to the R_DATA have no effect.
Messages that were not completely received due to a transmission abort is not copied into EQADC_SSIRDR.
Table 18-21. System Clock Divide Factor for Baud Clock (continued)
BR[0:3] System Clock Divide Factor
1