Freescale Semiconductor MPC5565, Reference Manual

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SRAM
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 14-5
14.7.1 Example Code
To initialize SRAM correctly, use the store multiple word ( stmw) instruction to implement 64-bit writes
to all SRAM locations. The stmw instruction concatenates two 32-bit registers to implement a single
64-bit write.
The following example code illustrates the use of the stmw instruction to initialize the SRAM ECC bits.
init_RAM:
lis r11,0x4000 # base address of the SRAM, 64-bit word aligned
ori r11,r11,0 # not needed for this address but could be for others
li r12,640 # loop counter to get all of SRAM;
# 80k/4 bytes/32 GPRs = 640
mtctr r12
init_ram_loop:
stmw r0,0(r11) # write all 32 GPRs to SRAM
addi r11,r11,128 # inc the ram ptr; 32 GPRs * 4 bytes = 128
bdnz init_ram_loop # loop for 80k of SRAM
blr # done
14.8 Document Revision History
Table 14-4. Changes Between MPC5565RM Revisions 0.1 and 1
No changes since the last release.