Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
18-22 Freescale Semiconductor
18.3.2.8 eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISR n )
The EQADC_FISRs contain flag and status bits for each CFIFO and RFIFO pair. Writing 1 to a flag bit
clears it. Writing 0 has no effect. Status bits are read only. These bits indicate the status of the FIFO itself.
8–11 Reserved.
12
RFOIE n
RFIFO overflow interrupt enable n . Enables the eQADC to generate an interrupt request when the corresponding
RFOF n in EQADC_FISRn is asserted. Refer to Section 18.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5
(EQADC_FISRn) .”
Apart from generating an independent interrupt request for an RFIFO n overflow event, the eQADC also provides a
combined interrupt at which the result FIFO overflow Interrupt, the command FIFO underflow interrupt, and the
command FIFO trigger overrun interrupt requests of all CFIFOs are ORed. When RFOIE
n , CFUIE n, and TORIE n
are all asserted, this combined interrupt request is asserted whenever one of the following 18 flags becomes
asserted: RFOF
n, CFUF n , and TORF n (assuming that all interrupts are enabled). Refer to Section 18.4.7, “eQADC
eDMA/Interrupt Request ,” for details.
0 Disable overflow interrupt request
1 Enable overflow Interrupt request
13 Reserved.
14
RFDE n
RFIFO drain enable n . Enables the eQADC to generate an interrupt request (RFDS n is asserted) or eDMA request
(RFDS n is negated) when RFDF n in EQADC_FISRn (Refer to Section 18.3.2.8, “eQADC FIFO and Interrupt Status
Registers 0–5 (EQADC_FISRn) ”
)
is asserted.
0 Disable RFIFO drain eDMA or interrupt request
1 Enable RFIFO drain eDMA or interrupt request
Note: RFDE n must not be negated while an eDMA transaction is in progress.
15
RFDS n
RFIFO drain select n . Selects if an eDMA or interrupt request is generated when RFDF n in EQADC_FISRn (Refer
to Section 18.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn)
”)
is asserted. If RFDE n is
asserted, the eQADC generates an interrupt request when RFDS n is negated, or it generates an eDMA request
when RFDS n is asserted.
0 Generate interrupt request to move data from RFIF n to the system memory
1 Generate eDMA request to move data from RFIFO n to the system memory
Note: RFDS n must not be negated while an eDMA transaction is in progress.
Table 18-11. EQADC_IDCR n Field Descriptions (continued)
Field Description