Freescale Semiconductor MPC5565, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
19-66 Freescale Semiconductor
in the DSPI return the correct values when read, but writing to them has no affect. Writing to the
DSPI
x _TCR during module disable mode does not have an effect. Interrupt and DMA request signals
cannot be cleared while in the module disable mode.
19.4.10.2 Slave Interface Signal Gating
The DSPI module enable signal is used to gate slave interface signals such as address, byte enable,
read/write and data. This prevents toggling slave interface signals from consuming power unless the DSPI
is accessed.
19.5 Initialization and Application Information
19.5.1 How to Change Queues
DSPI queues are not part of the DSPI module, but the DSPI includes features in support of queue
management. Queues are primarily supported in SPI configuration. This section presents an example of
how to change queues for the DSPI.
1. The last command word from a queue is executed. The EOQ bit in the command word is set to
indicate to the DSPI that this is the last entry in the queue.
2. At the end of the transfer, corresponding to the command word with EOQ set is sampled, the EOQ
flag (EOQF) in the DSPI x _SR is set.
3. The setting of the EOQF flag disables both serial transmission, and serial reception of data, putting
the DSPI in the STOPPED state. The TXRXS bit is negated to indicate the STOPPED state.
4. The eDMA continues to fill TX FIFO until it is full or step 5 occurs.
5. Disable DSPI DMA transfers by disabling the DMA enable request for the DMA channel assigned
to TX FIFO and RX FIFO. This is done by clearing the corresponding DMA enable request bits in
the eDMA controller.
6. Ensure all received data in RX FIFO has been transferred to memory receive queue by reading the
RXCNT in DSPI x _SR or by checking RFDF in the DSPI x _SR after each read operation of the
DSPI x _POPR.
7. Modify DMA descriptor of TX and RX channels for “new” queues.
8. Flush TX FIFO by writing a 1 to the CLR_TXF bit in the DSPI x _MCR register and flush the RX
FIFO by writing a 1 to the CLR_RXF bit in the DSPI x _MCR register.
9. Clear transfer count either by setting CTCNT bit in the command word of the first entry in the new
queue or via CPU writing directly to SPI_TCNT field in the DSPI x _TCR.
10. Enable DMA channel by enabling the DMA enable request for the DMA channel assigned to the
DSPI TX FIFO, and RX FIFO by setting the corresponding DMA set enable request bit.
11. Enable serial transmission and serial reception of data by clearing the EOQF bit.