Freescale Semiconductor MPC5565, Reference Manual

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e200z6 Core Complex
MPC5565 Microcontroller Reference Manual, Rev. 1.0
3-24 Freescale Semiconductor
indicating the line contains valid data consistent with memory. Dirty cache lines have the D and V bits set,
indicating that the line has valid entries that have not been written to memory. In addition, a cache line can
be locked (L bit set) indicating the line is not available for replacement.
The cache must be invalidated after a hardware reset; a hardware reset does not invalidate the cache lines.
Following initial power-up, the cache contents are undefined. If the L, D, or V bits are set on any lines, the
software must invalidate cache before the cache is enabled.
Figure 3-15 illustrates the general flow of cache operation.
Figure 3-15. Cache Lookup Flow
To determine if the address is already allocated in the cache the following steps are taken:
1. The cache set index, virtual address bits A[20:26] are used to select one cache set. A set is defined
as the grouping of two lines (one from each way), corresponding to the same index into the cache
array.
2. The higher order physical address bits A[0:19] are used as a tag reference or used to update the
cache line tag field.
31 27 26 20
19 0
Index Tag data / Tag reference
MUX
0
1
Logical OR
HIT 1
HIT 0
Hit
Select
Set 0
Set 1
Set 127
•
•
•
Way 0
Way 1
Data or
instruction
Status DW0 DW1
Tag
Status DW0 DW1
•
•
•
•
•
•
•
•
•
•
•
•
Virtual address
Tag
Physical address
Set select
A[20:26]
Tag reference
A[0:19]