Freescale Semiconductor MPC5565, Reference Manual

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System Integration Unit (SIU)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
6-8 Freescale Semiconductor
6.2.1.6.3 Overruns
An overrun IRQ exists for each overrun flag bit in the overrun status register (SIU_OSR).
An overrun IRQ asserts when all of the following occur:
• Enable bit is set in the IRQ rising- and/or falling-edge event registers (SIU_IREER, SIU_IFEER)
• IRQ flag bit is set in the external interrupt status register (SIU_EISR)
• Bit is set in the overrun request enable and overrun status registers (SIU_ORER, SIU_OSR)
• Rising- or falling-edge event triggers an interrupt request
The SIU outputs one overrun IRQ bit that is the logical OR of all of the IRQ overrun bits.
Refer to the following sections for more information:
Section 6.3.1.4, “External Interrupt Status Register (SIU_EISR) ”
Section 6.3.1.7, “Overrun Status Register (SIU_OSR) ”
Section 6.3.1.8, “Overrun Request Enable Register (SIU_ORER) ”
6.2.1.6.4 Edge-Detect Events
An IRQ asserts when an:
• Edge-detect event is enabled
• Edge-detect event occurs
To assert an IRQ when an edge-detect event occurs:
1. Set the enable bit in the IRQ rising- and falling-edge event enable registers
(SIU_IREER, SIU_IFEER)
2. Clear the enable bits for the DMA transfer and interrupt request enable register (SIU_DIRER)
The IRQ bit is set in the external IRQ status register (SIU_EISR) when an edge-detect event occurs for
that IRQ.
Refer to the following sections for more information:
Section 6.3.1.4, “External Interrupt Status Register (SIU_EISR) ”
Section 6.3.1.9, “IRQ Rising-Edge Event Enable Register (SIU_IREER) ”
Section 6.3.1.10, “IRQ Falling-Edge Event Enable Register (SIU_IFEER) ”