Freescale Semiconductor MPC5565, Reference Manual

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MPC5565 Reference Manual Addendum, Rev. 2
Addendum for Revision 1.0
Freescale Semiconductor 12
Table 10-9. MPC5565
Interrupt Request
Sources/Page 10-23
Note:
Update the note at the end of this table as follows:
The INTC has no spurious vector support. Therefore, if an asserted peripheral or software
settable interrupt request (whose PRI value in INTC_PSRn is higher than the PRI value in
INTC_CPR) negates before the interrupt request to the processor for that peripheral or software
settable interrupt request is acknowledged, the interrupt request to the processor still can assert
or remain asserted for that peripheral or software settable interrupt request. If the interrupt
request to the processor does assert or does remain asserted:
• The interrupt vector will correspond to that peripheral or software settable interrupt request.
• The PRI value in the INTC_CPR will be updated with the corresponding PRI value in
INTC_PSRn.
Furthermore, clearing the peripheral interrupt request's enable bit in the peripheral or,
alternatively, setting its mask bit has the same consequences as clearing its flag bit.Setting its
enable bit or clearing its mask bit while its flag bit is asserted has the same effect on the INTC
as an interrupt event setting the flag bit.
Section 10.4.2.1.4, “Priority
Comparator Submodule”/
Page 10-25
Add the following paragraph to this section: One consequence of the priority comparator design
is that once a higher priority interrupt is captured, it must be acknowledged by the CPU before a
subsequent interrupt request of even higher priority can be captured. For example, if the CPU is
executing a priority level 1 interrupt, and a priority level 2 interrupt request is captured by the
INTC, followed shortly by a priority level 3 interrupt request to the INTC, the level 2 interrupt must
be acknowledged by the CPU before a new level 3 interrupt will be generated.
Section 10.5.5.2, “Ensuring
Coherency”/ Page 10-32
Move the content of this section under a new heading Section 10.5.5.2.1, “Interrupt with Blocked
Priority”.
Add the following paragraph to this section:
Section 10.5.5.2.2: Raised Priority Preserved
Before the instruction after the GetResource system service executes, all pending transactions
have completed. These pending transactions can include an ISR for a peripheral or software
settable interrupt request whose priority was equal to or lower than the raised priority. Also,
during the epilog of the interrupt exception handler for this preempting ISR, the raised priority
has been restored from the LIFO to PRI in INTC_CPR. The shared coherent data block now can
be accessed coherently. Following figure shows the timing diagram for this scenario, and the
table explains the events. The example is for software vector mode, but except for the method of
retrieving the vector and acknowledging the interrupt request to the processor, hardware vector
mode is identical.
Table 1. MPC5565RM Rev 1.0 addendum (continued)
Location Description