Freescale Semiconductor MPC5565, Reference Manual

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System Integration Unit (SIU)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 6-9
6.3 Memory Map and Register Definition
Table 6-5 is the address map for the SIU registers. All register addresses shown are an offset of the SIU
base address.
Table 6-5. SIU Register Address Map
Address Name Description Bits
Base = 0xC3F9_0000 Reserved
Base + 0x0004 SIU_MIDR MCU ID register 32
Base + 0x0008 Reserved
Base + 0x000C SIU_RSR Reset status register 32
Base + 0x0010 SIU_SRCR System reset control register 32
Base + 0x0014 SIU_EISR SIU external interrupt status register 32
Base + 0x0018 SIU_DIRER DMA/interrupt request enable register 32
Base + 0x001C SIU_DIRSR DMA/interrupt request select register 32
Base + 0x0020 SIU_OSR Overrun status register 32
Base + 0x0024 SIU_ORER Overrun request enable register 32
Base + 0x0028 SIU_IREER IRQ rising-edge event enable register 32
Base + 0x002C SIU_IFEER IRQ falling-edge event enable register 32
Base + 0x0030 SIU_IDFR IRQ digital filter register 32
Base + 0x0034–Base + 0x003F Reserved
Base + 0x0040–Base + 0x020C SIU_PCR0–SIU_PCR230 Pad configuration registers 0–230 16
Base + 0x020E–Base + 0x05FF Reserved
Base + 0x0600–Base + 0x06D5 SIU_GPDO0–SIU_GPDO213 GPIO pin data output registers 0–213 8
Base + 0x06D6–Base + 0x07FF Reserved
Base + 0x0800–Base + 0x08D5 SIU_GPDI0–SIU_GPDI213 GPIO pin data input registers 0–213 8
Base + 0x08D6–Base + 0x08FF Reserved
Base + 0x0900–Base + 0x0903 SIU_ETISR eQADC trigger input select register 32
Base + 0x0904–Base + 0x0907 SIU_EIISR External IRQ input select register 32
Base + 0x0908–Base + 0x090B SIU_DISR DSPI input select register 32
Base + 0x090C–Base + 0x097F Reserved
Base + 0x0980 SIU_CCR Chip configuration register 32
Base + 0x0984 SIU_ECCR External clock control register 32
Base + 0x0988 SIU_CARH Compare A high register 32
Base + 0x098C SIU_CARL Compare A low register 32
Base + 0x0990 SIU_CBRH Compare B high register 32