Enhanced Time Processing Unit (eTPU)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
17-26
Freescale Semiconductor
Table 17-11. ETPU_TBCR Field Descriptions
Field
Description
0–2
TCR2CTL
TCR2 clock and gate control are part of the TCR2 clocking system. These bits determine the clock source
for TCR2 before the prescaler. TCR2 can count on any detected edge of the TCRCLK signal or use it for
gating the system clock divided by 8. After reset, the TCRCLK signal rising edge is selected. TCR2 can also
be clocked by the system clock divided by 8. TCR2CTL also determines the TCRCLK edge selected for angle
tooth detection in angle mode. Refer to the
eTPU Reference Manual
for more information. TCR2 clock
sources are listed in the following table.
3–4
TCRCF
TCRCLK signal filter control. Controls the TCRCLK digital filter determining whether the TCRCLK signal
input (after a synchronizer) is filtered with the same filter clock as the channel input signals or uses the
system clock divided by 2, and also whether the TCRCLK digital filter works in integrator mode or two sample
mode. The following table describes TCRCLK filter clock/mode.
For more information, refer to the
eTPU Reference Manual
.
TCR2CTL
AM = 0
(TCR2 Clock)
AM = 1
(Angle Tooth Detection)
000
Gated DIV8 clock (system clock / 8). When
the external TCRCLK signal is low, the
DIV8 clock is blocked, preventing it from
incrementing the TCR2 prescaler. When
the external TCRCLK signal is high, TCR2
prescaler is incremented at the frequency
of the system clock divided by 8.
Refer to Note
1
1
Do not use these settings with AM = 1 (Angle Mode).
001
Rise transition on TCRCLK signal
increments TCR2 prescaler.
Rising edge
010
Fall transition on TCRCLK signal
increments TCR2 prescaler.
Falling edge
011
Rise or fall transition on TCRCLK signal
increments TCR2 prescaler.
Rising or falling edge
100
DIV8 clock (system clock / 8)
Refer to Note
101
Reserved
110
Reserved
111
TCR2CTL shuts down TCR2 clocking,
except on Angle Mode. TCR2 can also
change as STAC client.
TCRCF
Filter Input
Filter Mode
00
System clock divided by 2
two sample
01
Filter clock of the channels
two sample
10
System clock divided by 2
integration
11
Filter clock of the channels
integration
Summary of Contents for MPC5565
Page 18: ...MPC5565 Microcontroller Reference Manual Devices Supported MPC5565 MPC5565 RM Rev 1 0 09 2007...
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Page 553: ...Flash Memory MPC5565 Microcontroller Reference Manual Rev 1 0 13 38 Freescale Semiconductor...
Page 559: ...SRAM MPC5565 Microcontroller Reference Manual Rev 1 0 14 6 Freescale Semiconductor...
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Page 1153: ...Calibration MPC5565 Microcontroller Reference Manual Rev 1 0 B 8 Freescale Semiconductor...
