Freescale Semiconductor MPC5565, Reference Manual

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External Bus Interface (EBI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
12-48 Freescale Semiconductor
Table 12-18 lists the bytes required on the data bus for read cycles. The bytes indicated as ‘—’ are not
required during that read cycle.
Table 12-19 lists the patterns of the data transfer for write cycles when accesses are initiated by the MCU.
The bytes indicated as ‘—’ are not driven during that write cycle.
Table 12-18. Data Bus Requirements for Read Cycles
Transfer
Size
TSIZ[0:1]
1
1
TSIZ is not enabled on the MPC5565.
Address 32-Bit Port Size 16-Bit Port Size
2
2
Also applies when DBM = 1 for 16-bit data bus mode.
A[30] A[31] D[0:7] D[8:15] D[16:23] D[24:31] D[0:7] D[8:15]
Byte 01 0 0 OP0 — — — OP0 —
01 0 1 — OP1 — — — OP1
01 1 0 — — OP2 — OP2 —
01 1 1 — — — OP3 — OP3
16-bit 10 0 0 OP0 OP1 — — OP0 OP1
10 1 0 — — OP2 OP3 OP2 OP3
32-bit 00 0 0 OP0 OP1 OP2 OP3 OP0/OP2
3
3
This case consists of two 16-bit external transactions, the first fetching OP0 and OP1, the second fetching OP2 and
OP3.
OP1/OP3
Table 12-19. Data Bus Contents for Write Cycles
Transfer
Size
TSIZ[0:1]
1
1
TSIZ is not enabled on the MPC5565.
Address 32-Bit Port Size 16-Bit Port Size
2
2
Also applies when DBM = 1 for 16-bit data bus mode.
A[30] A[31] D[0:7] D[8:15] D[16:23] D[24:31] D[0:7] D[8:15]
Byte 01 0 0 OP0 — — — OP0 —
01 0 1 OP1 OP1 — — — OP1
01 1 0 OP2 — OP2 — OP2 —
01 1 1 OP3 OP3 — OP3 — OP3
16-bit 10 0 0 OP0 OP1 — — OP0 OP1
10 1 0 OP2 OP3 OP2 OP3 OP2 OP3
32-bit 00 0 0 OP0 OP1 OP2 OP3 OP0/OP2
3
3
This case consists of two 16-bit external transactions, the first writing OP0 and OP1, the second writing OP2 and OP3.
OP1/OP3