Freescale Semiconductor MPC5565, Reference Manual

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Frequency Modulated Phase Locked Loop and System Clocks (FMPLL)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
11-18 Freescale Semiconductor
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PLLREF
PLL clock reference source. Determined at reset, this bit indicates whether the PLL reference source is an
external clock or a crystal reference. This bit is cleared in dual controller mode and bypass mode. Refer to
Chapter 4, “Reset ,” for details on how to configure the system clock mode during reset.
0 External clock reference chosen.
1 Crystal clock reference chosen.
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LOCKS
Sticky FMPLL lock status bit. A sticky indication of FMPLL lock status. LOCKS is set by the lock detect circuitry
when the FMPLL acquires lock after one of the following:
• System reset
• Write to the FMPLL_SYNCR that modifies the MFD and PREDIV bits
• Enable frequency modulation
Whenever the FMPLL loses lock, LOCKS is cleared. LOCKS remains cleared even after the FMPLL relocks,
until one of the three previously-stated conditions occurs. Furthermore, if the LOCKS bit is read when the
FMPLL simultaneously loses lock, the bit does not reflect the current loss of lock condition.
If operating in bypass mode, LOCKS remains cleared after reset. In crystal reference, external reference, and
dual-controller mode, LOCKS is set after reset.
0 PLL has lost lock since last system reset, a write to FMPLL_SYNCR to modify the MFD and PREDIV bit
fields, or frequency modulation enabled.
1 PLL has not lost lock since last system reset, a write to FMPLL_SYNCR to modify the MFD and PREDIV
bit fields, or frequency modulation enabled.
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LOCK
PLL lock status bit. Indicates whether the FMPLL has acquired lock. If the LOCK bit is read when the FMPLL
simultaneously loses lock or acquires lock, the bit does not reflect the current condition of the FMPLL.
If operating in bypass mode, LOCK remains cleared after reset. Refer to the frequency as defined in the
MPC5565 Microcontroller Data Sheet for the lock/unlock range.
0 PLL is unlocked.
1 PLL is locked.
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LOCF
Loss-of-clock flag. This bit provides the interrupt request flag. This is a write 1 to clear (w1c) bit; to clear the
flag, the user must write a 1 to the bit. Writing 0 has no effect. Asserting reset clears the flag. This flag is sticky
in the sense that if clocks return to normal after the flag has been set, the bit remains set until cleared by either
writing 1 or asserting reset.
0 Interrupt service not requested
1 Interrupt service requested
Table 11-5. FMPLL_SYNSR Field Descriptions (continued)
Field Description