Boot Assist Module (BAM)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
15-10
Freescale Semiconductor
15.3.2.3.2
Serial Boot Mode FlexCAN and eSCI Configuration
In serial boot mode, the BAM program configures FlexCAN A and eSCI A to receive messages. The
CNRXA and RXDA signals are configured as inputs to the FlexCAN and eSCI modules. The CNTXA
signal is configured as an output from the FlexCAN module. The TXDA signal of the eSCI A remains
configured as GPIO input. The BAM program writes 0x0000_0000_0000_0000 to the e200z6 core
timebase registers (TB), and enables the e200z6 core watchdog timer to use the system clock and to cause
a reset after a time-out period of 3 x 2
28
system clock cycles.
Refer to
for examples of time out periods.
In serial boot mode the FlexCAN controller is configured to operate at a baud (bit) rate equal to the system
clock frequency divided by 60 with one message buffer (MB) using the standard 11-bit identifier format
detailed in the CAN 2.0A specification.
Refer to
Section 21.4.5.4, “Protocol Timing
,” for information on FlexCAN bit rate generation.
Coming out of reset, the default system clock is 1.5 times the crystal frequency. The baud rate with PLL
enabled is equal to the crystal frequency divided by 40.
Refer to
Chapter 11, “Frequency Modulated Phase Locked Loop and System Clocks (FMPLL)
,” for more
information.
shows FlexCAN operation at reset.
The BAM ignores the following errors:
•
Bit 1 errors
•
Bit 0 errors
•
Acknowledge errors
•
Cyclic redundancy code errors
•
Form errors
•
Stuffing errors
•
TX error counter errors
•
Rx error counter errors
All data received, regardless of errors, is echoed out on the CNTXA signal.
NOTE
The host computer must compare the ‘echoed data’ to the sent data and
restart the process if an error is detected.
Table 15-6. BAM FlexCAN Frequency at Reset (FMPLL Enabled out of Reset)
FMPLL Clock Mode
System Clock Frequency (f
sys
)
after Reset
Serial Boot Mode Frequency
1
(FlexCAN Baud Rate)
1
Serial boot mode frequency is set in software as the system clock frequency divided by 60.
Crystal reference mode or
External reference mode
1.5 x crystal reference frequency
(f
ref_crystal
)
2
2
Crystal reference frequency is set at 8–20 MHz.
Crystal reference frequency
divided by 40
Dual controller mode
2 x EXTCLK
EXTCLK divided by 30
Summary of Contents for MPC5565
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Page 1153: ...Calibration MPC5565 Microcontroller Reference Manual Rev 1 0 B 8 Freescale Semiconductor...
