Freescale Semiconductor MPC5565, Reference Manual

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Preface
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 21-17
21.3.3.4.2 RX 14 Mask (CAN x _RX14MASK)
The CAN x _RX14MASK register has the same structure as the RX global mask register and is used to
mask message buffer 14. Access to this register is unrestricted. Note that CANx_RX14MASK is
unaffected by soft reset (which occurs when CAN_MCR[SOFTRST] is asserted).
• Address offset: 0x14
• Reset value: 0x1FFF_FFFF
21.3.3.4.3 RX 15 Mask (CAN x _RX15MASK)
The CAN x _RX15MASK register has the same structure as the RX global mask register and is used to
mask message buffer 15. Access to this register is unrestricted. Note that CANx_RX15MASK is
unaffected by soft reset (which occurs when CAN_MCR[SOFTRST] is asserted).
• Address offset: 0x18
• Reset value: 0x1FFF_FFFF
21.3.3.5 RX Individual Mask Registers (CAN x _RXIMR0 – CAN x _RXIMR63)
By asserting the CAN x _MCR[MBFEN] bit, the CAN x _RXIMR[0-63] registers are used as acceptance
masks for received frame IDs, in both standard and extended ID formats. One mask register is provided
for each message buffer for individual ID masking per message buffer. The meaning of each mask bit is
the following:
• Mask bit = 0: The corresponding incoming ID bit is a “don’t care.”
• Mask bit = 1: The corresponding ID bit is checked against the incoming ID bit, to see if a match
exists.
The Individual Rx Mask Registers are implemented in RAM, so they are not affected by reset and must be
explicitly initialized prior to any reception. Furthermore, they can only be accessed by the CPU while the
module is in freeze mode. Out of freeze mode, write accesses are blocked and read accesses will return
all 0s. Furthermore, if the MBFEN bit in the MCR register is negated, any read or write operation to these
RXIMR
n registers results in access error.
Address: Base + 0x0880–0x097F Access: User R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0
MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16
W
Reset U U U U U U U U U U U U U U U U
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
MI15 MI14 MI13 MI12 MI11 MI10 MI9 MI8 MI7 MI6 MI5 MI4 MI3 MI2 MI1 MI0
W
Reset U U U U U U U U U U U U U U U U
Figure 21-7. RX Individual Mask Registers (CANx_RXIMR0 – CANx_RXIMR63)