Freescale Semiconductor MPC5565, Reference Manual

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MPC5565 Reference Manual Addendum, Rev. 2
Addendum for Revision 1.0
Freescale Semiconductor 14
Section 6.3.1.118 “Pad
Configuration Register 218
(SIU_PCR218)”
• Change PA field from two bits to one bit
• Figure 6-119: Change note 2 to “... set the PA field to 0b0.”
• Table 6-119. PCR218 “PA Field Definition” change as shown below:
0b0 FCK
0b1 AN[15]
Section 11.3.1.1
Synthesizer Control Register
(FMPLL_SYNCR)
Changed the last note in PREDIV field description from
“To use the 8-20 MHz OSC, the PLL predivider must be configured for divide-by-two operation
by tying PLLCFG[2] low (set PREDIV to 0b000).” to
“When using an 8 to 20 MHz reference clock (crystal or external clock), PLLCFG[2] should be
set low for devices that have a PLLCFG[2] pin. This sets the default predivider (PREDIV) to
0b000. To use a crystal or external reference greater than 20 MHz (up to 40 MHz), the PLL
predivider must be configured for divide-by-2 operation by setting PLLCFG[2] high. This sets the
default predivider (PREDIV) to 0b001. After reset, PREDIV must not be configured to a value
less than divide-by-2 (with a 40 MHz crystal/reference).”
Table 1. MPC5565RM Rev 1.0 addendum (continued)
Location Description