Freescale Semiconductor MPC5565, Reference Manual

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MPC5565 Register Map
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor A-51
RFIFO 2 register 2 EQADC_RF2R2 32-bit Base + 0x0388
RFIFO 2 register 3 EQADC_RF2R3 32-bit Base + 0x038C
Reserved — — Base + (0x0390–0x03BF)
RFIFO 3 register 0 EQADC_RF3R0 32-bit Base + 0x03C0
RFIFO 3 register 1 EQADC_RF3R1 32-bit Base + 0x03C4
RFIFO 3 register 2 EQADC_RF3R2 32-bit Base + 0x03C8
RFIFO 3 register 3 EQADC_RF3R3 32-bit Base + 0x03CC
Reserved — — Base + (0x03D0–0x03FF)
RFIFO 4 register 0 EQADC_RF4R0 32-bit Base + 0x0400
RFIFO 4 register 1 EQADC_RF4R1 32-bit Base + 0x0404
RFIFO 4 register 2 EQADC_RF4R2 32-bit Base + 0x0408
RFIFO 4 register 3 EQADC_RF4R3 32-bit Base + 0x040C
Reserved — — Base + (0x0410–0x043F)
RFIFO 5 register 0 EQADC_RF5R0 32-bit Base + 0x0440
RFIFO 5 register 1 EQADC_RF5R1 32-bit Base + 0x0444
RFIFO 5 register 2 EQADC_RF5R2 32-bit Base + 0x0448
RFIFO 5 register 3 EQADC_RF5R3 32-bit Base + 0x044C
Reserved — — Base + (0x0450–0x07FF)
ADC0 control register ADC0_CR
No memory mapped access
ADC1 control register ADC1_CR
ADC time stamp control register ADC_TSCR
ADC time base counter register ADC_TBCR
ADC0 gain calibration constant register ADC0_GCCR
ADC1 gain calibration constant register ADC1_GCCR
ADC0 offset calibration constant register ADC0_OCCR
ADC1 offset calibration constant register ADC1_OCCR
Reserved — — Base + (0x0800–0xFFF8_FFFF)
Deserial / Serial Peripheral Interface (DSPIx)
Chapter 19, “Deserial Serial Peripheral Interface (DSPI)
0xFFF9_4000 (DSPI B)
0xFFF9_8000 (DSPI C)
0xFFF9_C000 (DSPI D)
Module configuration register DSPIx_MCR 32-bit Base + 0x0000
Reserved — — Base + (0x0004–0x0007)
Transfer count register DSPIx_TCR 32-bit Base + 0x0008
Table A-2. MPC5565 Detailed Register Map (continued)
Register Description Register Name
Used
Size
Address