Nexus
MPC5565 Microcontroller Reference Manual, Rev. 1.0
24-84
Freescale Semiconductor
24.14.2.11.3 NXDM Register Access via JTAG
Access to Nexus register resources is enabled by loading a single instruction (NEXUS_ACCESS) into the
JTAG Instruction Register (IR). This IR is part of the IEEE
®
1149.1
TAP controller within the NXDM
modules. Refer to
Section 23.4.4, “JTAGC Instructions
.”
After the JTAG NEXUS_ACCESS instruction has been loaded, the JTAG port allows tool/target
communications with all Nexus registers according to the map in
Reading/writing of a Nexus register then requires two (2) passes through the data-scan (DR) path of the
JTAG state machine (refer to
Chapter 23, “IEEE 1149.1 Test Access Port Controller (JTAGC)
”).
1. The first pass through the DR selects the Nexus register to be accessed by providing an index
(refer to
), and the direction (read/write). This is achieved by loading an 8-bit value into
the JTAG data register (DR). This register has the following format:
2. The second pass through the DR then shifts the data in or out of the JTAG port, lsb first.
a) During a read access, data is latched from the selected Nexus register when the JTAG state
machine passes through the capture-DR state.
b) During a write access, data is latched into the selected Nexus register when the JTAG state
machine passes through the update-DR state.
24.14.3 Functional Description
24.14.4 Enabling NXDM Operation
The NXDM module is enabled by loading a single instruction (ACCESS_AUX_TAP_DMA as shown in
) into the JTAG instruction register (IR), and then loading the corresponding OnCE OCMD
register with the NEXUS_ACCESS instruction (refer to
). After it is enabled, the module will
be ready to accept control input via the JTAG pins.
The Nexus module is disabled when the JTAG state machine reaches the test-logic-reset state. This state
can be reached by the assertion of the JCOMP pin or by cycling through the state machine using the TMS
pin. The Nexus module will also be disabled if a power-on reset (POR) event occurs.
Access: R/W
7
6
5
4
3
2
1
0
R
Nexus Register Index
R/W
W
Reset
Figure 24-65. JTAG DR for NEXUS Register Access
Table 24-55. DR Read/Write Encoding
Nexus Register Index
Read/Write (R/W)
0 Read
1 Write
Summary of Contents for MPC5565
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