Freescale Semiconductor MPC5565, Reference Manual

Page: 1030 / 1153

Nexus
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 24-37
24.11.0.1 Port Configuration Register (PCR)
The Port Configuration Register (PCR) controls the basic port functions for all Nexus modules in a
multi-Nexus environment. This includes clock control and auxiliary port width. All bits in this register are
writable only once after system reset.
Figure 24-14. Port Configuration Register
NOTE
The CSC and PCR Registers exist in a separate module at the SoC level in
a multi-Nexus environment. If the Zen Nexus3 module is the only Nexus
module, these registers are not implemented and the Zen Nexus3 defined
Development Control Register 1 (DC1) is used to control Nexus port
functionality.
1
The CSC and PCR registers are shown in this table as part of the Nexus programmer’s model. They are only
present at the top level Nexus3 controller (NPC), not in the NZ6C3 module. The device’s CSC register is readable
through Nexus3, but the PCR is shown for reference only.
OPC
0
MCK_EN
M
C
K_DIV
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nexus Reg# - PCR_INDEX; R/W; Reset - 0x0
Table 24-25. Port Configuration Register Fields
PCR[31] OPC OPC — Output Port Mode Control
0 = Reduced Port Mode configuration (minimum # nex_mdo[n:0]
pins)
1 = Full Port Mode configuration (max# nex_mdo[n:0] pins defined
by SOC)
PCR[30] — Reserved for future functionality
PCR[29] MCK_EN MCK_EN — MCKO Clock enable
0 = nex_mcko is disabled
1 = nex_mcko is enabled
PCR[28:26] MCK_DIV MCK_DIV — MCKO Clock Divide Ratio (read note that follows this table)
000 = nex_mcko is 1x processor clock frequency.
001 = nex_mcko is 1/2x processor clock frequency.
010 = Reserved (defaults to 1/2x processor clock frequency.)
011 =
nex_mcko is 1/4x processor clock frequency.
100–110 = Reserved (defaults to 1/2x processor clock frequency.)
111 =
nex_mcko is 1/8x processor clock frequency.
PCR[25:0] — Reserved for future functionality