Freescale Semiconductor MPC5565, Reference Manual

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Introduction
MPC5565 Microcontroller Reference Manual, Rev. 1.0
1-8 Freescale Semiconductor
– Six chip selects, expandable to 64 with external demultiplexers
– Programmable frame size, baud rate, clock delay, and clock phase on a per-frame basis
– Modified SPI mode for interfacing to peripherals with longer setup time requirements
— Deserial serial interface (DSI)
– Pin reduction by hardware serialization and deserialization of eTPU and eMIOS channels
– Chaining of DSI submodules
– Triggered transfer control and change in data transfer control (for reduced EMI)
• Two enhanced serial communication interface (eSCI) modules
— UART mode provides NRZ format and half or full duplex interface
— eSCI bit rate up to 1 Mb/s
— Advanced error detection, and optional parity generation and detection
— Word length programmable as 8 or 9 bits
— Separately enabled transmitter and receiver
— LIN support
— DMA support
— Interrupt request support
• Three FlexCANs
— 64 message buffers each
— Full implementation of the CAN protocol specification, Version 2.0B
— Based on and including all existing features of the Freescale TouCAN module
— Programmable acceptance filters
— Individual receive filtering per message buffer
— Short latency time for high-priority transmit messages
— Arbitration scheme according to message ID or message buffer number
— Listen-only mode capabilities
— Programmable clock source: system clock or oscillator clock
— Reception queue possible by setting more than one receive message buffer with the same ID
— Backwards compatibility with previous FlexCAN modules
• Nexus development interface (NDI)
— Per IEEE
®
-ISTO 5001-2003
— Real-time development support for Power Architecture core and eTPU engine through Nexus
class 3 (some class 4 support)
— Data trace of eDMA accesses
— Read and write access
— Configured via the IEEE
®
1149.1 (JTAG) port
— High-bandwidth mode for fast message transmission
— Reduced bandwidth mode for reduced pin usage