Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Time Processing Unit (eTPU)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
17-8 Freescale Semiconductor
17.1.4.6 Microengine
The eTPU microengine is a simple RISC implementation that performs each instruction in a microcycle
of two system clocks, while pre-fetching the next instruction through an instruction pipeline. Instruction
execution time is constant for the arithmetic logic unit (ALU) unless it gets wait states from SDM
arbitration.
Microcode is stored in shared code memory (SCM) that is 32 bits wide. The microengine instruction set
provides basic arithmetic and logic operations, flow control (jumps and subroutine calls), SDM access, and
channel configuration and control. The instruction formats are defined in such a way that allow particular
combinations of two or three of these operations with unconflicting resources to be executed in parallel in
the same microcycle, thus improving performance.
The microengine also has an independent multiply/divide/MAC unit that performs these complex
operations in parallel with other microengine instructions.
Channel functionality is integrated into the instruction set through channel control operations and
conditional branch operations, which support jumps/calls on channel-specific conditions. This allows
quick and terse channel configuration and control code, contributing to reduced service time.
17.1.4.7 Debug Interface
Nexus level 3 debug support is available through the eTPU Nexus development interface (NDEDI). Refer
to
Chapter 24, “Nexus Development Interface .”
17.1.5 Features
The eTPU includes these distinctive features:
• Up to 32 channels for each eTPU engine: each channel is associated with an I/O signal pair
— Enhanced input digital filters on the input pins for improved noise immunity. The eTPU digital
filter can use two samples, three samples, or work in continuous mode.
— Orthogonal channels, except for channel 0: each channel can perform any time function. Each
time function can be assigned to more than one channel at a given time, so each signal can have
any functionality. Channel 0 has the same capabilities of the others, but can also work with
special angle counter logic.
— A link service request allows activation of a channel thread by request of another channel, even
between eTPU engines.
— A host service request allows activation of a channel thread by the device core request.
— Each channel has an event mechanism that supports single and double action functionality in
various combinations. It includes two 24-bit capture registers, two 24-bit match registers,
24-bit greater-equal or equal-only comparator.