Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 18-19
Address: EQAD 0x050 (EQADC_CFCR0)
EQAD 0x052 (EQADC_CFCR1)
EQAD 0x054 (EQADC_CFCR2)
EQAD 0x056 (EQADC_CFCR3)
EQAD 0x058 (EQADC_CFCR4);
EQAD 0x05A (EQADC_CFCR5) Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0
MODE n
0 0 0 0
W SSE n CFINV n
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 18-7. eQADC CFIFO Control Registers (EQADC_CFCR n )
Table 18-9. EQADC_CFCR n Field Descriptions
Field Description
0–4 Reserved.
5
SSE n
CFIFO single-scan enable bit n . Used to set the SSS n bit, as described in Section 18.3.2.8, “eQADC FIFO and
Interrupt Status Registers 0–5 (EQADC_FISRn) .” Writing a 1 to SSE n sets the SSS n if the CFIFO is in single-scan
mode. When SSS n is already asserted, writing a 1 to SSE n has no effect. If the CFIFO is in continuous-scan mode
or is disabled, writing a 1 to SSE n does not set SSS n . Writing a 0 to SSE n has no effect. SSE n always is read as 0.
0 No effect.
1 Set the SSS
n bit.
6
CFINV n
CFIFO invalidate bit n . Causes the eQADC to invalidate all entries of CFIFO n . Writing a 1 to CFINV n resets the value
of CFCTR n in the EQADC_FISR register (refer to Section 18.3.2.8, “eQADC FIFO and Interrupt Status Registers
0–5 (EQADC_FISRn) .” Writing a 1 to CFINV n also resets the push next data pointer, transfer next data pointer to the
first entry of CFIFO n in Figure 18-35 . Reading CFINV n always returns a 0. Writing a 0 has no effect.
0 No effect.
1 Invalidate all of the entries in the corresponding CFIFO.
Note: Writing CFINV n only invalidates commands stored in CFIFO n ; previously transferred commands that are
waiting for execution (commands stored in the ADC command buffers) are executed, and the results are stored
in the RFIFO.
Note: Do not write to CFINV n unless MODE n is disabled, and CFIFO status is IDLE.
7 Reserved.
8–11
MODE n
[0:3]
CFIFO operation mode n . Selects the CFIFO operation mode for CFIFO n . Refer to Section 18.4.3.5, “CFIFO Scan
Trigger Modes
,”
for more information on CFIFO trigger mode.
Note: If MODE n is not disabled, it must not be changed to any other mode besides disabled. If MODE n is disabled
and the CFIFO status is IDLE, MODE n can be changed to any other mode.
12–15 Reserved.
Table 18-10. CFIFO Operation Mode Table
MODE n [0:3] CFIFO Operation Mode
0b0000 Disabled
0b0001 Software trigger, single scan
0b0010 Low level gated external trigger, single scan
0b0011 High level gated external trigger, single scan