Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Direct Memory Access (eDMA)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
9-20 Freescale Semiconductor
9.2.2.15 eDMA Channel n Priority Registers (EDMA_CPR n )
When the fixed-priority channel arbitration mode is enabled (EDMA_CR[ERCA] = 0), the contents of
these registers define the unique priorities associated with each channel within a group. The channel
priorities are evaluated by numeric value; that is, 0 is the lowest priority, 1 is the next higher priority, then
2, 3, etc. If software chooses to modify channel priority values, then the software must ensure that the
channel priorities contain unique values, otherwise a configuration error is reported. The range of the
priority value is limited to the values of 0 through 15. When read, the GRPPRI bits of the EDMA_CPR
n
register reflect the current priority level of the group of channels in which the corresponding channel
resides. GRPPRI bits are not affected by writes to the EDMA_CPR
n registers. The group priority is
assigned in the EDMA_CR.
Refer to Figure 9-2 and Table 9-2 for the EDMA_CR definition.
Channel preemption is enabled on a per-channel basis by setting the ECP bit in the EDMA_CPR n register.
Channel preemption allows the executing channel’s data transfers to be temporarily suspended in favor of
starting a higher priority channel. After the preempting channel has completed all of its minor loop data
transfers, the preempted channel is restored and resumes execution. After the restored channel completes
one read/write sequence, it is again eligible for preemption. If any higher priority channel is requesting
service, the restored channel is suspended and the higher priority channel is serviced. Nested preemption
(attempting to preempt a preempting channel) is not supported. After a preempting channel begins
execution, it cannot be preempted. Preemption is only available when fixed arbitration is selected for both
group and channel arbitration modes.
Address: Base + 0x100 + n Access: User R/W
0 1 2 3 4 5 6 7
R
ECP
0 GRPPRI
CHPRI
W
Reset 0 0 —
1
1
The reset value for the group and channel priority fields,
GRPPRI[0–1] and CHPRI[0–3] is the channel number
for the priority register;
EDMA_CPR31[GRPPRI] = 0b01 and
EDMA_CPR31[CHPRI] = 0b1111.
Figure 9-17. eDMA Channel n Priority Register (EDMA_CPR n )