Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Direct Memory Access (eDMA)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
9-18 Freescale Semiconductor
9.2.2.14 eDMA Error Register (EDMA_ERL)
The EDMA_ERL provides a bit map for the 32 channels signaling the presence of an error for each
channel. EDMA_ERL maps to channels 31-0.
The eDMA engine signals the occurrence of a error condition by setting the appropriate bit in this register.
The outputs of this register are enabled by the contents of the EDMA_EEIR, then logically summed across
groups of 16 and 32 channels to form several group error interrupt requests which is then routed to the
interrupt controller. During the execution of the interrupt service routine associated with any DMA errors,
it is software’s responsibility to clear the appropriate bit, negating the error interrupt request. Typically, a
write to the EDMA_CER in the interrupt service routine is used for this purpose. Recall the normal DMA
channel completion indicators, setting the transfer control descriptor DONE flag and the possible assertion
of an interrupt request, are
not affected when an error is detected.
The contents of this register can also be polled and a non-zero value indicates the presence of a channel
error, regardless of the state of the EDMA_EEIR. The EDMA_ESR[VLD] bit is a logical OR of all bits in
this register and it provides a single bit indication of any errors. The state of any given channel’s error
indicators is affected by writes to this register; it is also affected by writes to the EDMA_CER. On writes
to EDMA_ERL, a 1 in any bit position clears the corresponding channel’s error status. A 0 in any bit
position has no affect on the corresponding channel’s current error status. The EDMA_CER is provided
so the error indicator for a
single channel can easily be cleared.
Address: Base + 0x0024 Access: User R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
INT
31
INT
30
INT
29
INT
28
INT
27
INT
26
INT
25
INT
24
INT
23
INT
22
INT
21
INT
20
INT
19
INT
18
INT
17
INT
16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
INT
15
INT
14
INT
13
INT
12
INT
11
INT
10
INT
09
INT
08
INT
07
INT
06
INT
05
INT
04
INT
03
INT
02
INT
01
INT
00
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 9-14. eDMA Interrupt Request Low Register (EDMA_IRQRL)
Table 9-14. EDMA_IRQRL Field Descriptions
Field Description
0–31
INT
n
eDMA interrupt request n.
0 The interrupt request for channel n is cleared.
1 The interrupt request for channel n is active.