Freescale Semiconductor MPC5565, Reference Manual

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Frequency Modulated Phase Locked Loop and System Clocks (FMPLL)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 11-9
11.1.4 FMPLL Modes of Operation
The FMPLL operational mode is configured during reset. For devices in the 324 (with or without the 496
assembly) package, the FMPLL operating mode defaults to crystal reference mode. If you change the
FMPLL to a different mode for devices that use these packages, the RSTCFG and PLLCFG[0:1] package
pins must be driven to the state for the new mode from the time RSTOUT asserts until it negates. As shown
in
Table 11-3 , if RSTCFG is not asserted during reset, the state of the PLLCFG package pins is ignored,
and the FMPLL operates in the default crystal reference mode. The table also shows that to enter any other
mode, RSTCFG must be asserted during reset.
Table 11-1 shows clock mode selection during reset configuration for the 324 (with or without the 496
assembly) pin package. Additional information on reset configuration options for the FMPLL are in
Chapter 4, “Reset .”
11.1.4.1 Crystal Reference (Default Mode)
In crystal reference mode, the FMPLL receives an input clock frequency (F
ref_crystal)
from the crystal
oscillator circuit (EXTAL_EXTCLK) and the pre-divider, and multiplies the frequency to create the
FMPLL output clock. The user must supply a crystal oscillator that is within the appropriate input
frequency range, the crystal manufacture’s recommended external support circuitry, and a short signal
route from the MCU to the crystal.
The external support circuitry for the crystal oscillator is shown in Figure 11-7 . Example component
values are shown as well. Note that the actual circuit should be reviewed with the crystal manufacturer. A
block diagram illustrating crystal reference mode is shown in
Figure 11-4 .
Table 11-1. Clock Mode Selection in 324 (with or without the 496 assembly) Package
Clock Mode
Package Pins
Synthesizer Status Register
(FMPLL_SYNSR)
1
Bits
1
Refer to Section 11.3.1.2, “Synthesizer Status Register (FMPLL_SYNSR) ” for more information on these bits.
RSTCFG PLLCFG[0] PLLCFG[1] MODE PLLSEL PLLREF
Crystal reference
(default mode)
1 PLLCFG pins ignored.
1 1 1
0 1 0
External reference 0 0 1 1 1 0
Bypass mode 0 0 0 0 0 0
Dual-controller mode 0 1 1 1 0 0