Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 18-37
18.3.3 On-Chip ADC Registers
This section describes a list of registers that control on-chip ADC operation. The ADC registers are not
part of the CPU accessible memory map. These registers can only be accessed indirectly through
configuration commands. There are five non memory mapped registers per ADC, five for ADC0 and five
for ADC1. The address, usage, and access privilege of each register is shown in
Table 18-25 and
Table 18-26 . Data written to or read from reserved areas of the memory map is undefined.
Their assigned addresses are the values used to set the ADC_REG_ADDRESS field of the read/write
configuration commands bound for the on-chip ADCs. These are halfword addresses. Further, the
following restrictions apply when accessing these registers:
• Registers ADC0_CR, ADC0_GCCR, and ADC0_OCCR can only be accessed by configuration
commands sent to the ADC0 command buffer.
• Registers ADC1_CR, ADC1_GCCR, and ADC1_OCCR can only be accessed by configuration
commands sent to the ADC1 command buffer.
• Registers ADC_TSCR and ADC_TBCR can be accessed by configuration commands sent to the
ADC0 command buffer or to the ADC1 command buffer. A data write to ADC_TSCR through a
configuration command sent to the ADC0 command buffer writes the same memory location as
when writing to it through a configuration command sent to the ADC1 command buffer. The same
is valid for ADC_TBCR.
NOTE
Simultaneous write accesses from the ADC0 and ADC1 command buffers
to ADC_TSCR or to ADC_TBCR are not allowed.
Table 18-25. ADC0 Registers
ADC0
Register
Address Use Access
0x00 ADC0 Address 0x00 is used for conversion command
messages.
0x01 ADC0 Control Register (ADC0_CR) Write/Read
0x02 ADC Time Stamp Control Register (ADC_TSCR)
1
1
This register is also accessible by configuration commands sent to the ADC1 command buffer.
Write/Read
0x03 ADC Time Base Counter Register (ADC_TBCR)
1
Write/Read
0x04 ADC0 Gain Calibration Constant Register (ADC0_GCCR) Write/Read
0x05 ADC0 Offset Calibration Constant Register (ADC0_OCCR) Write/Read
0x06–0xFF Reserved —