Freescale Semiconductor MPC5565, Reference Manual

Page: 548 / 1153

Flash Memory
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 13-33
13.4.2.5 Flash Shadow Block
The flash shadow block is a memory-mapped block in the flash memory map. Program and erase of the
shadow block are enabled only when FLASH_MCR[PEAS] = 1. After the user has begun an erase
operation on the shadow block, the operation cannot be suspended to program the main address space and
vice-versa. The user must terminate the shadow erase operation to program or erase the main address
space.
NOTE
If an erase of user space is requested, and a suspend is done with attempts
to erase suspend program shadow space, this attempted program is directed
to user space as dictated by the state of FLASH_MCR[PEAS]. Likewise an
attempted erase suspended program of user space, while the shadow space
is being erased, is directed to shadow space as dictated by the state of
FLASH_MCR[PEAS].
The shadow block cannot utilize the RWW feature. After an operation is started in the shadow block, a
read cannot be done to the shadow block, or any other block. Likewise, after an operation is started in a
block in low/mid/high address space, a read cannot be done in the shadow block.
The shadow block contains information on how the lock registers are reset. The first and second words can
be used for reset configuration words. All other words can be used for user defined functions or other
configuration words.
The shadow block can be locked/unlocked against program or erase by using the FLASH_LMLR or
FLASH_SLMLR discussed in
Section 13.3.2, “Register Descriptions .”
Programming of the shadow row has similar restrictions to programming the array in terms of how ECC
is calculated. Refer to
Section 13.4.2.3, “Flash Programming ” for more information. Only one program is
allowed per 64 bit ECC segment between erases. Erase of the shadow row is done similarly as an array
erase. Refer to
Section 13.4.2.4, “Flash Erase ” for more information.
13.4.2.6 Censorship
Censorship logic disables access to internal flash based on the censorship control word value and the
BOOTCFG[0:1] bits in the SIU_RSR. This prevents modification of the FLASH_BIUAPR bitfields
associated with all masters except the core based on the censorship control word value, the
BOOTCFG[0:1] bits in the SIU_RSR, and the EXTM bit in the EBI_MCR. Also, censorship logic sets the
boot default value to external-with-external-master access disabled based on the value of the censorship
control word and a TCU input signal.
13.4.2.6.1 Censorship Control Word
The censorship control word is a 32-bit value located at the base address of the shadow row plus 0x1E0.
The flash module latches the value of the control word prior to the negation of system reset. Censorship
logic uses the value latched in the flash module to disable access to internal flash, disable the NDI, prevent
modification of the FLASH_BIUAPR bitfields, and/or set the boot default value.