Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor
18-17
18.3.2.4
eQADC CFIFO Push Registers 0–5 (EQADC_CFPR
n
)
The EQADC_CFPRs provide a mechanism to fill the CFIFOs with command messages from the command
queues. Refer to
Section 18.4.3, “eQADC Command FIFOs
,” for more information on the CFIFOs and to
Section 18.4.1.2, “Message Format in eQADC
,” for a description on command message formats.
0b1011
2049
17075.00
0b1100
4097
34141.67
0b1101
8193
68275.00
0b1110
16385
136541.67
0b1111
32769
273075.00
Address: Base + 0x010 (EQADC_CFPR0)
Base + 0x014 (EQADC_CFPR1);
Base + 0x018 (EQADC_CFPR2)
Base + 0x01C (EQADC_CFPR3)
Base + 0x020 (EQADC_CFPR4)
Base + 0x024 (EQADC_CFPR5)
Access: Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
CF_PUSH
n
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
CF_PUSH
n
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 18-5. eQADC CFIFO Push Registers 0–5 (EQADC_CFPR
n
)
Table 18-7. EQADC_CFPR
n
Field Descriptions
Field
Description
0–31
CF_PUSH
n
[0:31]
CFIFO push data
n
. When CFIFO
n
is not full, writing to the whole word or any bytes of EQADC_CFPR
n
pushes
the 32-bit CF_PUSH
n
value into CFIFO
n
. Writing to the CF_PUSH
n
field also increments the corresponding
CFCTR
n
value by one in
Section 18.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn)
.”
When the CFIFO
n
is full, the eQADC ignores any write to the CF_PUSH
n
. Reading the EQADC_CFPR
n
always
returns 0.
Note:
Only whole words must be written to EQADC_CFPR. Writing halfwords or bytes to EQADC_CFPR pushes
the entire 32-bit CF_PUSH field into the CFIFO, but undefined data fills the areas of CF_PUSH that were
not specifically designated as target locations for the write.
Table 18-6. Minimum Required Time to Valid ETRIG (continued)
DFL[0:3]
Minimum Clock Count
Minimum Time (ns)
(System Clock = 120MHz)
Summary of Contents for MPC5565
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