Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Serial Communication Interface (eSCI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 20-27
20.4.5.3 Data Sampling
The receiver uses a sampling clock to sample the RXD input signal at the 16 times the baud-rate frequency.
This sampling clock is called the RT clock. To adjust for baud rate mismatch, the RT clock (Refer to
Figure 20-17 ) is re-synchronized:
• After every start bit.
• After the receiver detects a data bit change from logic 1 to logic 0. This data bit change is detected
when a majority of data samples return a valid logic 1 and a majority of the next data samples return
a valid logic 0. Data samples are taken at RT8, RT9, and RT10, as shown in
Figure 20-17 .
To locate the start bit, eSCI data recovery logic performs an asynchronous search for a logic 0 preceded
by three logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
Figure 20-17. Receiver Data Sampling
To verify the start bit and to detect noise, the eSCI data recovery logic takes samples at RT3, RT5, and
RT7.
Table 20-18 summarizes the results of the start bit verification samples.
If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins.
Table 20-18. Start Bit Verification
RT3, RT5, and RT7 Samples Start Bit Verification Noise Flag
000 Yes 0
001 Yes 1
010 Yes 1
011 No 0
100 Yes 1
101 No 0
110 No 0
111 No 0
RT clock
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
Start bit
qualification
Start bit
verification
Data
sampling
RT1
RT1
RT1 RT1
RT1
RT1
RT1 RT1
RT1 RT3 RT5 RT7 RT9 RT11 RT13 RT15 RT1 RT3
RT2 RT4 RT6 RT8 RT10 RT12 RT14 RT16 RT2 RT4
Reset
RT clock
RT clock
count
RXD input
signal
samples
Start bit LSB