Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Serial Communication Interface (eSCI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 20-31
20.4.5.5.2 Fast Data Tolerance
Figure 20-20 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10
instead of RT16 but is still sampled at RT8, RT9, and RT10.
Figure 20-20. Fast Data
For an 8-bit data character, data sampling of the stop bit takes the receiver 154 RT cycles, as is shown
below:
With the misaligned character shown in Figure 20-20 , the receiver counts 154 RT cycles at the point when
the count of the transmitting device is 10 bit times x 16 RT cycles = 160 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit
character with no errors is 3.40%, as is shown below:
For a 9-bit data character, data sampling of the stop bit takes the receiver 170 RT cycles, as shown below:
With the misaligned character shown in Figure 20-20 , the receiver counts 170 RT cycles at the point when
the count of the transmitting device is 11 bit times x 16 RT cycles = 176 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit
character with no errors is 3.40%, as is shown below:
20.4.5.6 Receiver Wake-up
The receiver can be put into a standby state, which disregards all input requests targeted for other receivers
in multiple-receiver systems. Setting the receiver wake-up bit (RWU) in eSCI control register 1
RT1
Receiver
RT clock
RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16
STOP IDLE or next frame
Data samples
9 bit times 16 RT cycles 10 RT cycles +
×
154 RT cycles =
160 – 154
160
--------------------------
100
×
3.40% =
10 bit times 16 RT cycles 10 RT cycles +
×
170 RT cycles =
176 – 170
176
-------------------------- 100
×
3.40% =