Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Serial Communication Interface (eSCI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
20-36 Freescale Semiconductor
LIN LWAKE A wake-up character has been received from a LIN frame. The LIN
wake-up (LWAKE) flag is set when the LIN hardware receives a
wake-up character sent by one of the LIN slaves. This occurs only
when the LIN bus is in sleep mode. Clear the LWAKE flag by writing a
1 to the bit. ESCI x _SR[18] WUIE
LIN STO The response of the slave has been too slow (slave timeout). The
slave timeout (STO) flag is set during an RX frame when the LIN slave
has not transmitted all requested data bytes before the specified
timeout period. Clear the STO flag by writing a 1 to the bit. ESCI x _SR[19] STIE
LIN PBERR Physical bus error detected. If the RXD input remains at the same
value for 15 cycles after a transmission has started, the LIN hardware
sets the physical bus error (PBERR) flag. Clear the PBERR flag by
writing a 1 to the bit. ESCI x _SR[20] PBIE
LIN CERR CRC error detected. If an RX frame has the CRC checking flag set,
and the two CRC bytes do not match the calculated CRC pattern, the
CRC error (CERR) flag is set. Clear the CERR flag by writing a 1 to
the bit. ESCI x _SR[21] CIE
LIN CKERR Checksum error detected. If an RX frame has the checksum checking
flag set and the last byte does not match the calculated checksum, the
checksum error (CKERR) flag is set. Clear the CKERR flag by writing
a 1 to the bit. ESCI x _SR[22] CKIE
LIN FRC LIN frame completed. The frame complete (FRC) flag is set after the
last byte of a TX frame is transmitted, or after the last byte of an RX
frame is received. The FRC flag indicates that the next frame can be
set up. Clear the FRC flag by writing a 1 to the bit.
Note: The last byte of an outgoing TX frame or incoming RX frame
indicates that the checksum comparison occurred.
Note: It is possible to set the FRC flag before the DMA controller has
completed transferring the last byte from the eSCI port to
system memory. Do not set the FRC flag if the frame will be
processed. For frames that will be processed, use the DMA
controller interrupt.
ESCI x _SR[23] FCIE
LIN OVFL ESCIx_LRR overflow. The overflow (OVFL) flag is set when a byte is
received in the ESCI
x _LRR before the previous byte is read. Since the
system is responsible for reading the register before the next byte
arrives, this condition indicates a problem with CPU load. The OVFL
flag is cleared by writing a 1 to the bit.
ESCI x _SR[31] OFIE
Table 20-21. eSCI Interrupt Flags, Sources, Mask Bits, and Descriptions (continued)
Interrupt
Source
Flag Description Source
Local
Enable